Silicon Bridge Die Tiling for Large Fine-Node Chip Packages
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Solution Overview
Problem
Conventional techniques for manufacturing heterogeneous-chip packages are limited by the size of silicon interposers and assembly processes, which restrict the size of the package and lead to complex layouts and reduced yield rates, especially when using fine node chips with node lengths smaller than 7 nm.
Innovation Solution
The use of silicon bridges fabricated using the same wafer processes as the base die and fine node chips, with thinness and fine routing capabilities, allows for larger heterogeneous-chip packages by providing interconnections between base die and fine node chips, enabling robust electrical connections and higher yields, and utilizing an organic substrate for processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon interposer techniques are used to interconnect base die and fine node chips, then electrical connections can be established, but the size of the heterogeneous-chip package is limited and manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection structure into modular components: base die, fine node chips, and silicon bridge segments. These segmented components can be independently fabricated and then assembled, allowing the package size to scale beyond the limitations of conventional monolithic silicon interposers while maintaining reliable electrical connections through the modular bridge segments.
Solution Approach 2:
The silicon bridge acts as an intermediary component between the base die and fine node chips. This mediator enables electrical interconnection while allowing the package to expand in size, as the bridge can be fabricated in segments and assembled in a scalable manner unlike conventional direct interposer techniques.
2Reliability
If conventional silicon interposer techniques are used for interconnection, then electrical connections can be made, but device complexity and manufacturing difficulty increase
Solution Approach 1:
By segmenting the silicon bridge into manageable sections that can be fabricated using standard wafer processes and then assembled, the patent reduces layout complexity. Each segment can be designed and manufactured independently, avoiding the need for complex monolithic interposer layouts while maintaining reliable electrical connections.
Solution Approach 2:
The patent changes the fabrication parameters by using the same wafer fabrication processes for the silicon bridge as for the base die and fine node chips. This parameter alignment simplifies manufacturing by eliminating the need for specialized interposer fabrication processes, reducing device complexity while ensuring reliable electrical connections.
3Reliability
If conventional interconnection methods are used, then electrical connections can be established, but yield rates decrease for fine node chips with node lengths smaller than 7 nm
Solution Approach 1:
The patent changes the fabrication parameter alignment by manufacturing the silicon bridge using the same wafer processes and parameters as the base die and fine node chips. This ensures that all components are fabricated under identical process conditions, which is critical for maintaining high yield rates when working with fine node chips having node lengths of 7 nm and smaller, while still achieving reliable electrical connections.
Data Source
AI summary
Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.