Embedded Silicon Bridge Glass Substrates for Bump Variation Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor device miniaturization during die-tiling packaging faces challenges in managing bump-thickness variations during assembly, which affects the reliability and performance of the packaged semiconductor apparatus.
Innovation Solution
The implementation of embedded multi-chip interconnect bridges (EMIBs) within inorganic layers, specifically using silicon bridges embedded in glass substrates with through-glass vias and a redistribution layer, to mitigate warpage and facilitate heterogeneous die integration, miniaturization, and high performance while maintaining yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are miniaturized during die-tiling packaging, then device size is reduced and performance is improved, but bump-thickness variations occur during assembly which affects reliability
Solution Approach 1:
The patent divides the packaging structure into modular components including separate die elements, bump structures, and interconnect layers. This segmentation allows independent optimization of each component and facilitates assembly by enabling modular integration of miniaturized devices while maintaining control over bump thickness through dedicated processing steps for each module.
Solution Approach 2:
The patent employs parameter changes in the bump structure design, including varying bump heights, materials, and formation methods to compensate for thickness variations. By adjusting these parameters during the assembly process, the patent maintains reliable electrical and mechanical connections despite the challenges of miniaturization, thereby preserving assembly reliability while achieving device size reduction.
2Stability of the object's composition
If embedded multi-chip interconnect bridges are implemented within inorganic layers, then warpage is reduced and heterogeneous die integration is facilitated, but device complexity increases
Solution Approach 1:
The patent utilizes composite material structures combining organic and inorganic layers, as well as different semiconductor materials for heterogeneous die integration. The embedded interconnect bridges are formed within composite packaging substrates that integrate multiple materials with complementary properties, enabling warpage control through material selection and stacking while achieving complex die integration functions.
Solution Approach 2:
The patent implements nested structures where interconnect bridges are embedded within packaging layers, which themselves are integrated into larger device assemblies. This nesting approach allows multiple functional layers to be stacked and integrated vertically, reducing lateral footprint and managing complexity through hierarchical organization of components.
3Productivity
If through-glass vias and redistribution layers are used in glass substrates, then miniaturization and high performance are enabled, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary formation of through-glass vias and redistribution layers during substrate processing before die attachment. This preliminary action allows precise control over via positioning and layer formation, enabling miniaturization and high-performance interconnects while managing manufacturing complexity through pre-planned, pre-formed structures that simplify subsequent assembly steps.
Solution Approach 2:
The patent replaces traditional mechanical wiring methods with vertically stacked interconnect structures formed through glass substrates. This substitution enables higher density and performance by utilizing the third dimension for signal routing, while standardized via formation processes and redistribution layer patterns manage the complexity of manufacturing these advanced interconnect structures.
Data Source
AI summary
A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.