Silicon Bridge Layer for Logic-Memory Interconnects
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Solution Overview
Problem
Current 3D IC packaging techniques, particularly those using interposers, are costly and do not effectively support die-to-die functionality such as logic to memory communication, while two-dimensional integration is limited by physical density constraints.
Innovation Solution
A semiconductor package method involving a silicon bridge layer with redistribution layers (RDLs) that facilitates electrical communication between dies, ensuring effective power and ground connectivity, and includes an electrical test to verify the functionality of each die before attachment, thereby supporting logic to memory die communication at reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If interposer techniques are used for bonding dies to reduce form factor, then device miniaturization is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the interposer layer from the packaging structure and replaces it with a substrate that directly bonds to multiple dies. This elimination of the interposer intermediate layer reduces manufacturing complexity and cost while achieving the same form factor reduction goal through direct die-to-substrate bonding arrangements.
Solution Approach 2:
The patent introduces a substrate as a new intermediary that directly bonds to multiple dies, replacing the traditional interposer. This substrate serves as the mediating element that enables die-to-die connections without requiring expensive interposer materials and processes, thereby reducing manufacturing cost while maintaining miniaturization benefits.
2Adaptability or versatility
If traditional 3D packaging methods are used, then die stacking is achieved, but support for logic to memory die functionality is limited
Solution Approach 1:
The substrate is designed with multiple bond pads and connection points that can accommodate different die types (logic, memory, etc.) with various pin configurations. This universal substrate structure enables flexible die-to-die functionality including logic to memory communication without requiring complex specialized packaging structures for each die combination.
Solution Approach 2:
The patent segments the packaging structure into a substrate with distinct bond pad regions that can independently connect to different dies. This segmentation allows each die to be optimally configured for its specific function (logic or memory) while the substrate provides the flexible interconnection framework needed to support various die-to-die functional arrangements without increasing overall packaging complexity.
3Reliability
If electrical testing is performed after complete assembly, then final product verification is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent performs electrical testing on individual dies before they are bonded to the substrate. This preliminary action identifies defective dies early in the manufacturing process, allowing them to be discarded before assembly. By testing beforehand rather than after complete assembly, the patent reduces manufacturing time and cost by avoiding the need to disassemble and retest fully assembled units, while still ensuring final product reliability.
Data Source
AI summary
A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.