External Silicon Bridge Interconnect for Multi-Chip Carrier Assembly
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Solution Overview
Problem
The increasing complexity and size of semiconductor chips lead to higher manufacturing defect densities and yield losses, while traditional packaging methods struggle to achieve fast communication between multiple dies due to cumbersome assembly processes and the need for through substrate vias (TSVs) or complex interposers.
Innovation Solution
An advanced packaging structure using external silicon bridges with high signal density wiring, connected via solder balls between chips and a carrier, which eliminates the need for TSVs and simplifies the assembly process by using a carrier with good thermal and coefficient of thermal expansion (CTE) characteristics to support the bridges and reduce stress during assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through substrate vias (TSVs) are used to connect multiple chips in a chip stack, then high-speed communication between chips is achieved, but the device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent extracts the complex TSV process from the packaging structure by using external silicon bridges with surface-mounted connections. The bridges are attached to the chip surfaces using conventional soldering techniques, eliminating the need for through-substrate vias and their associated complex manufacturing steps while maintaining high-speed signal transmission capability.
Solution Approach 2:
The patent introduces silicon bridges as intermediary elements between chips and the package substrate. These bridges serve as mediator components that provide high-speed interconnects without requiring TSVs, simplifying the overall packaging structure while enabling fast communication between multiple chips.
2Speed
If silicon interposers are used to connect multiple chips, then high-speed communication is enabled, but the assembly process becomes cumbersome requiring TSV processes and temporary carriers
Solution Approach 1:
The patent removes the cumbersome TSV processes and temporary carrier requirements by using external silicon bridges that can be mounted directly onto chip surfaces using conventional soldering. This extraction of complex processes simplifies the assembly workflow while maintaining the high-speed communication capability provided by interposer-based approaches.
Solution Approach 2:
The patent employs disposable temporary carriers that are used only during the bridge attachment process and then discarded. These simple, single-use carriers enable easy positioning and soldering of the silicon bridges without the need for complex reusable fixtures or permanent temporary support structures.
3Ease of manufacture
If embedded silicon bridges are incorporated into the package substrate, then TSVs are eliminated, but the package substrate complexity increases and creates separate part numbers for each combination
Solution Approach 1:
The patent segments the bridge structure from the package substrate by using external, detachable silicon bridges rather than embedding them into the substrate. This segmentation allows the bridges to be attached separately to chips and then mounted as a complete assembly, preventing the substrate from becoming complex and requiring separate part numbers for different bridge combinations.
Solution Approach 2:
The patent creates a universal package substrate design that can accommodate different combinations of silicon bridges and chips through standardized external bridge attachments. This universal substrate platform eliminates the need for custom-substrate variations, reducing part number proliferation while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed inter-chip communication without the complexity of TSVs or interposers, reduces yield loss, and minimizes stress on fragile silicon bridges during assembly, while providing thermal support for the chips and bridges.
Implementation Method 1
Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element
Implementation Method 2
a carrier with good thermal and coefficient of thermal expansion (CTE) characteristics to support the bridges and reduce stress during assembly
Implementation Method 3
a carrier with good thermal and coefficient of thermal expansion (CTE) characteristics to support the bridges and reduce stress during assembly
Data Source
AI summary
A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.