Semiconductor Package Structure With Silicon Bridge and Recessed Underfill
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Solution Overview
Problem
Existing semiconductor packaging structures are inadequate in providing efficient electrical connections and mechanical support while minimizing package size and reducing thermal stress.
Innovation Solution
A semiconductor package structure incorporating an interposer substrate with a recess and a connecting element, such as a silicon bridge, for fine pitch electrical connections and improved die-to-die connections, along with an underfill layer to manage thermal stress and protect the connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures are used, then manufacturing simplicity is maintained, but electrical connection efficiency and mechanical support are inadequate
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the semiconductor die and the package substrate. This interposer provides a platform for fine pitch electrical connections through bump structures, improving signal transmission efficiency while distributing mechanical stress. The interposer acts as a mediator that resolves the contradiction by enabling reliable electrical connections without requiring direct complex integration between the die and package substrate.
Solution Approach 2:
The package structure is segmented into distinct functional layers: the semiconductor die, the interposer substrate with recess, bump structures for electrical connections, underfill layer, and package substrate. This segmentation allows each component to be optimized independently for its specific function, improving overall electrical connection efficiency while maintaining manufacturing feasibility through modular assembly.
2Strength
If larger package structures are used, then mechanical support and thermal management are improved, but package size increases
Solution Approach 1:
The interposer substrate features a localized recess structure that provides mechanical support and stress distribution exactly where needed - at the connection interface between the die and interposer. This localized reinforcement improves mechanical strength without requiring the entire package structure to be enlarged, thus maintaining compact overall dimensions while providing adequate mechanical support at critical locations.
3Reliability
If through silicon vias are used for connections, then electrical connectivity is achieved, but thermal stress and manufacturing complexity increase
Solution Approach 1:
The design extracts and eliminates the need for through silicon vias by using bump structures formed on the interposer substrate surface. This extraction removes the harmful thermal stress associated with deep via holes penetrating through silicon, while still achieving reliable electrical connectivity through the bump connections. The solution takes out the problematic TSV approach and replaces it with a surface-level bump connection method.
4Speed
If fine pitch connections are implemented, then signal transmission speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The interposer substrate serves as a mediator that enables fine pitch connections with relaxed manufacturing precision requirements. The interposer's larger substrate area provides a stable platform for forming precise bump patterns, and the recess structure ensures proper alignment. This intermediary approach allows fine pitch signal transmission without directly requiring ultra-precise alignment between the die and final package substrate, thus achieving high speed with manageable manufacturing precision.
Data Source
AI summary
A semiconductor package structure is provided, which includes a substrate, a connecting element, first and second conductive structures, a first semiconductor device, a second semiconductor device, a first underfill layer, and a first package layer. The connecting element is disposed below a top surface of the substrate. The first conductive structures are disposed over the connecting element. The second conductive structures are disposed over the substrate. The first conductive structures are surrounded by the second conductive structures. The first and second semiconductor devices are disposed on the substrate and electrically connected to each other through the connecting element and the first and second conductive structures. The first underfill layer is disposed between the first and second semiconductor devices and the substrate. The first underfill layer partially extends below the top surface. The first package layer surrounds the first and second semiconductor devices and the first underfill layer.