Thin Silicon Cap Gate Stack for Oxygen-Blocked High-k Annealing
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Solution Overview
Problem
The formation of FinFETs faces challenges in avoiding the adverse diffusion of oxygen into semiconductor fins, which can lead to an increase in the thickness of the interfacial layer and affect the quality of the high-k dielectric layer during the annealing process.
Innovation Solution
In-situ deposition of a silicon cap layer on a metal-containing capping layer, which is further deposited on a high-k gate dielectric layer, without exposing the layers to oxygen, followed by an annealing process to improve the quality of the high-k dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon cap layer is deposited to block oxygen diffusion, then the interfacial layer thickness increase is reduced, but the process complexity increases due to additional deposition steps
Solution Approach 1:
A silicon cap layer is deposited in advance before the annealing process to prevent oxygen diffusion into the high-k dielectric layer. This preliminary protective action ensures that when annealing occurs, oxygen cannot reach the interfacial layer, thereby preventing unwanted thickening while maintaining process control.
Solution Approach 2:
The silicon cap layer acts as an intermediary barrier between the oxygen-containing annealing environment and the high-k dielectric layer. This intermediate layer blocks the harmful oxygen diffusion path while allowing the annealing process to proceed, thus protecting the underlying structures without requiring direct modification of the annealing conditions.
2Reliability
If annealing is performed to improve high-k dielectric layer quality, then the dielectric quality is enhanced, but oxygen diffuses into the semiconductor fin increasing interfacial layer thickness
Solution Approach 1:
The silicon cap layer is deposited before annealing to preemptively counteract the oxygen diffusion that would otherwise occur during the annealing process. This preliminary protective measure allows the annealing to proceed for quality enhancement while the cap layer simultaneously prevents the harmful oxygen ingress that would thicken the interfacial layer.
Solution Approach 2:
The silicon cap layer serves as a mediating barrier that enables the annealing process to occur without its harmful side effects. It allows the beneficial thermal treatment to improve dielectric quality while blocking the harmful oxygen diffusion, thus decoupling the beneficial and harmful effects of annealing.
3Loss of time
If the silicon cap layer is made thinner to reduce process complexity, then the deposition time is reduced, but the oxygen blocking effectiveness decreases
Solution Approach 1:
The thickness of the silicon cap layer is optimized to a specific parameter range that provides sufficient oxygen blocking capability while minimizing deposition time. By carefully controlling the thickness parameter, the process achieves the necessary protective function without excessive material deposition, thus balancing time and effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The silicon cap layer effectively blocks oxygen diffusion, reducing the adverse increase in the interfacial layer thickness and maintaining the integrity of the high-k dielectric layer, thereby enhancing the process window for subsequent etching and gate electrode formation.
Implementation Method 1
The silicon cap layer effectively blocks oxygen diffusion, reducing the adverse increase in the interfacial layer thickness
Implementation Method 2
By in-situ depositing the silicon cap layer on the metal-containing capping layer, the adsorption of oxygen on the metal-containing capping layer is avoided
Implementation Method 3
followed by an annealing process to improve the quality of the high-k dielectric layer
Data Source
AI summary
A method includes forming a dummy gate stack on a semiconductor region, forming gate spacers on sidewalls of the dummy gate stack, removing the dummy gate stack to form a recess between the gate spacers, and forming a silicon oxide layer on the semiconductor region. The silicon oxide layer extends into the recess. A high-k dielectric layer is deposited over the silicon oxide layer, and a silicon layer is deposited over the high-k dielectric layer. The silicon layer extends into the recess. The high-k dielectric layer and the silicon layer are in-situ deposited in a same vacuum environment. The method further includes performing an annealing process on the silicon layer and the high-k dielectric layer, removing the silicon layer, and forming a gate electrode over the high-k dielectric layer. The gate electrode fills the recess.