Silicon Cap Layer for Uniform Salicide Formation
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Solution Overview
Problem
The formation of salicides in semiconductor devices can lead to silicon consumption and uneven silicon distribution, resulting in short circuits and malfunction due to insufficient silicon at the source and drain interfaces, as well as voids in the salicide layer caused by etching processes.
Innovation Solution
The use of cap layers composed of silicon, deposited over the source and drain features, provides additional silicon atoms to ensure a sufficient and uniform salicide layer thickness, preventing etching through and reducing resistance, thereby enhancing the yield and performance of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is deposited over source and drain features to form salicide, then conductivity between source and drain features and conductive lines is enhanced, but silicon atoms are consumed and insufficient silicon remains at the surface interface causing short circuits
Solution Approach 1:
A cap layer comprising silicon is deposited over the source and drain features before the metal layer is deposited. This preliminary deposition of silicon ensures sufficient silicon atoms are available at the surface interface to react with the metal layer during annealing, preventing etching through the salicide and avoiding short circuits while still achieving conductivity enhancement
2Ease of manufacture
If the etching process is used to remove unreacted metal, then unreacted metal is removed, but the salicide is etched through creating openings that form short circuits
Solution Approach 1:
The cap layer of silicon is deposited beforehand to provide excess silicon that compensates for silicon consumption during salicide formation. This ensures the salicide layer maintains sufficient thickness to prevent etching through during the subsequent etching process, cushioning against the harmful effect of potential short circuits
3Quantity of substance
If silicon atoms are unevenly concentrated in the source and drain features, then salicide formation occurs, but voids form in the salicide causing device malfunction
Solution Approach 1:
The cap layer comprising silicon is deposited uniformly over the source and drain features, providing homogeneous silicon distribution. This uniform silicon supply ensures even salicide formation across all features, preventing void formation and maintaining device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The inclusion of cap layers ensures a thicker, more uniform salicide layer, reducing the occurrence of short circuits and voids, thus increasing production yield and device reliability by providing sufficient silicon for the salicidation reaction and maintaining consistent silicon concentration.
Implementation Method 1
depositing a cap layer comprising silicon over the source and drain features
Implementation Method 2
The assembly is then annealed to form a salicide in a reaction between silicon atoms in the source and drain features and metal atoms in the metal layer
Implementation Method 3
The unreacted metal is then removed using an etching process
Data Source
AI summary
A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.