Silicon Cap Layer Prevents III-V Semiconductor Surface Decomposition
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Solution Overview
Problem
III-V compound semiconductors undergo surface decomposition and pitting during high temperature processing, which degrades their electrical characteristics and hinders the fabrication of high-performance semiconductor devices like MOSFETs, as existing methods lack effective and inexpensive solutions for preventing surface decomposition.
Innovation Solution
A thin silicon cap layer with a thickness of 10 Å to 400 Å is applied to III-V compound semiconductors, preventing surface decomposition and maintaining surface integrity during high temperature annealing, while also enabling effective dopant activation and improved dielectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature annealing is performed to electrically activate ion implanted dopants and improve dielectric properties, then electrical activation and dielectric properties are improved, but surface decomposition and pitting occur
Solution Approach 1:
A thin silicon cap layer (10-400 Å) is introduced as an intermediary protective layer between the III-V compound semiconductor surface and the high temperature processing environment. This cap layer acts as a mediator that prevents direct interaction between the semiconductor surface and harmful conditions, allowing high temperature annealing to proceed while protecting the surface from decomposition and pitting.
Solution Approach 2:
The silicon cap layer is deposited onto the III-V compound semiconductor surface before high temperature annealing processing. This preliminary protective action ensures that when the subsequent high temperature treatment is applied, the surface is already protected and can withstand the thermal processing without undergoing decomposition or pitting.
2Area of stationary object
If thick silicon films or silicon dioxide or silicon nitride are used as cap layers, then surface coverage is achieved, but severe surface pitting occurs
Solution Approach 1:
The critical parameter changed is the thickness of the silicon cap layer. By optimizing the thickness to a specific range (10-400 Å), the cap layer provides sufficient surface coverage and protection while maintaining the correct stoichiometry and preventing the formation of excessive silicon-rich phases that cause pitting. This parameter optimization resolves the contradiction between adequate coverage and prevention of harmful effects.
Solution Approach 2:
Different materials require different cap layer thicknesses to achieve optimal protection. The invention specifies precise thickness ranges for different cap layer materials (e.g., 10-400 Å for silicon, 50-200 Å for germanium) to achieve the right balance between protection and prevention of pitting, recognizing that local material properties dictate the appropriate protective layer characteristics.
3Reliability
If conventional cap layers are used to protect III-V compound semiconductors, then some surface protection is achieved, but they are either too thick causing pitting or too thin providing insufficient protection
Solution Approach 1:
The invention establishes specific thickness parameter ranges for different cap layer materials that optimize both protection effectiveness and pitting prevention. By defining these precise ranges (e.g., 10-400 Å for silicon caps), the method provides clear manufacturing guidelines that balance surface protection with prevention of thickness-related defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thin silicon cap layer effectively prevents surface pitting and maintains the integrity of III-V compound semiconductor surfaces, allowing for high temperature processing without decomposition, thereby enhancing the electrical properties and performance of semiconductor devices.
Implementation Method 1
Group V elements such as As evaporate from the surface of a III-V compound semiconductor upon high temperature annealing (greater than 800° C.), leaving surface defects including surface pitting
Implementation Method 2
forming a structure including a silicon layer having a thickness from 10 Å to 400 Å on a surface of a III-V compound semiconductor
Data Source
AI summary
A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.