Silicon Cap Formation for SiGe FinFET Germanium Outdiffusion Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing feature sizes for increased integration density, particularly with FinFETs, where fully strained channels improve performance but also introduce issues like interface trapping density and germanium outdiffusion, leading to defects and performance degradation.
Innovation Solution
A low-temperature process for forming a silicon cap layer over silicon germanium fins, including a pre-clean, sublimation, and deposition in a furnace, followed by an HCl etch to selectively remove amorphous silicon 'wings' and prevent germanium outdiffusion, thereby reducing defects and enhancing hole mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully strained channel architecture is used to improve FinFET performance, then device performance is improved, but interface trapping density increases causing performance degradation
Solution Approach 1:
A silicon cap layer is formed over the silicon germanium fin structure before subsequent processing steps. This preliminary capping action prevents germanium outdiffusion during high-temperature annealing processes, thereby reducing interface trapping density at the silicon-oxide interface while maintaining the fully strained channel architecture for improved device performance
Solution Approach 2:
The silicon cap layer acts as an intermediary barrier between the silicon germanium fin and the oxidizing environment. This intermediate silicon layer prevents direct interaction between germanium and oxygen, eliminating the formation of germanium oxide at the interface and reducing interface trapping density while preserving the strain-induced performance enhancement
2Productivity
If feature size is reduced to increase integration density, then integration density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The formation of the silicon cap layer modifies the physical and chemical parameters of the fin surface, creating a more stable structure that is less sensitive to dimensional variations. This parameter change enables better control of subsequent processing steps, maintaining manufacturing precision even as feature sizes are reduced to increase integration density
3Reliability
If germanium outdiffusion is prevented to reduce defects, then device reliability is improved, but process complexity increases
Solution Approach 1:
The silicon cap layer is formed as a preliminary protective layer before high-temperature processing steps. This single preliminary action prevents germanium outdiffusion during subsequent annealing and oxidation processes, improving device reliability without requiring multiple complex process steps or continuous monitoring
Solution Approach 2:
The silicon cap layer serves as a simple intermediary barrier that physically blocks germanium diffusion pathways. This straightforward mechanism prevents defect formation through a single structural addition rather than requiring complex process control measures, thereby improving reliability with minimal increase in process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved hole mobility, reduced channel resistance, better line-edge roughness, and stable threshold voltage without increasing interface trapping density, leading to enhanced performance of semiconductor devices.
Implementation Method 1
an HCl etch to selectively remove amorphous silicon 'wings' and prevent germanium outdiffusion
Implementation Method 2
sublimation, and deposition in a furnace
Data Source
AI summary
A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.