Silicon Cap Layer Annealing for Lower Interface Trap Charge
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Solution Overview
Problem
As semiconductor devices shrink in size, the short channel effect prevents further scaling down of planar field effect transistors, and p-type fully strained channel devices are susceptible to defects at the silicon cap layer interface, leading to increased interface trap charge density, leakage current, and channel resistance due to lattice mismatch and oxidation issues.
Innovation Solution
A method for fabricating semiconductor devices involves forming fins of different semiconductor materials, depositing a silicon cap layer over them, and performing a post-silicon-cap anneal to crystallize the cap layer and reduce interface trap charge, followed by a high-pressure anneal to further enhance channel properties, thereby improving hole mobility and reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon cap layer is formed over a p-type fully-strained channel to protect against oxidation, then oxidation protection is improved, but interface trap charge density increases leading to current leakage and increased channel resistance
Solution Approach 1:
An interfacial layer is introduced between the silicon cap layer and the p-type fully-strained channel to act as a mediator. This interfacial layer reduces the lattice mismatch and minimizes the generation of interface trap charges at the cap-channel interface, thereby maintaining the oxidation protection function while reducing harmful interface traps.
Solution Approach 2:
The lattice constant of the interfacial layer is specifically engineered to be intermediate between the silicon cap layer and the p-type channel, creating a gradual transition that reduces lattice mismatch. This parameter change in the interfacial layer's crystal structure reduces dislocation density and interface trap charge formation.
2Productivity
If geometry size of IC devices is shrunk to increase production efficiency, then productivity is improved, but device performance is substantially impacted due to increased defect sensitivity
Solution Approach 1:
The interfacial layer is specifically applied at the critical cap-channel interface region where lattice mismatch occurs, rather than uniformly throughout the entire device structure. This localized approach addresses the specific quality issue at the interface while maintaining the overall device scaling benefits.
3Speed
If p-type fully-strained channel devices are used to improve hole mobility, then hole mobility is improved, but channel resistance increases due to interface trap charge
Solution Approach 1:
The interfacial layer serves as a mediator that preserves the strain-induced hole mobility enhancement in the p-type channel while simultaneously reducing the interface trap charge that would otherwise increase channel resistance. The interfacial layer allows the strained channel to maintain its high mobility characteristics while minimizing parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces channel resistance by 5-10% and increases hole mobility, independent of channel length, by enhancing the crystallinity of the silicon cap layer and suppressing interface trap charge, leading to improved performance in p-type fully strained channel transistors.
Implementation Method 1
performing a post-silicon-cap anneal to crystallize the cap layer and reduce interface trap charge
Implementation Method 2
performing a post-silicon-cap anneal to crystallize the cap layer
Implementation Method 3
followed by a high-pressure anneal to further enhance channel properties
Data Source
AI summary
A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.