Silicon Capacitor Chip Layout for Semiconductor EMC Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving electromagnetic compatibility (EMC) characteristics due to high parasitic impedance and noise generation in signal transmission paths.
Innovation Solution
The semiconductor device integrates a silicon capacitor chip on the same package substrate as the IC chip, reducing connection path length and parasitic impedance by electrically connecting the silicon capacitor chip to the IC chip through a common ground terminal, and optimizing the layout to mitigate magnetic field interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor is mounted on a separate board or far from the IC chip, then the device complexity is reduced, but the parasitic impedance increases and EMC characteristics deteriorate
Solution Approach 1:
The patent merges the capacitor and IC chip mounting onto the same PCB board, placing them in close proximity to minimize the parasitic impedance of the connection path. This integration approach reduces the loop area for high-frequency currents, thereby improving EMC characteristics without significantly increasing overall device complexity.
Solution Approach 2:
The patent applies local quality optimization by specifically designing the capacitor and IC chip placement geometry to minimize parasitic inductance in the critical signal path. The capacitor is positioned adjacent to the IC chip with optimized trace routing, creating a localized low-impedance path for high-frequency currents while other parts of the board maintain standard design practices.
2Ease of manufacture
If the connection path between capacitor and IC chip is lengthened, then the layout flexibility improves, but the parasitic impedance increases and noise generation worsens
Solution Approach 1:
The patent optimizes the local geometry of the capacitor and IC chip placement to minimize parasitic inductance. The capacitor is positioned with its terminals oriented to create the shortest possible current loop path to the IC chip power and ground pins, reducing the area enclosed by high-frequency currents and thereby minimizing electromagnetic radiation and noise.
Solution Approach 2:
The patent utilizes three-dimensional placement strategies, considering the vertical stacking of components and traces on multiple PCB layers. By routing power and ground traces on adjacent layers directly beneath the capacitor and IC chip, the patent creates a compact electromagnetic coupling structure that minimizes parasitic impedance without constraining lateral layout flexibility.
3Measurement precision
If separate ground terminals are used for capacitor and IC chip, then the electrical connection precision improves, but the parasitic impedance increases
Solution Approach 1:
The patent merges the ground connections of the capacitor and IC chip into a common ground terminal or ground plane region. This shared ground reference minimizes the parasitic impedance of the ground path by providing a low-impedance return path for high-frequency currents, while maintaining precise electrical connections through optimized via and trace design to the common ground point.
Data Source
AI summary
According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.