Silicon Capacitor Structure Using TSV Recesses for Higher Density

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Solution Overview

Problem

Conventional silicon capacitors face challenges in size, density, and high temperature environment limitations, particularly in system-on-a-chip applications, limiting their suitability for high-Q and high-frequency applications.

Innovation Solution

A silicon capacitor structure is manufactured through a through-silicon via (TSV) process after the semiconductor front-end-of-line (FEOL) process, extending into the silicon substrate and avoiding high temperature influences, with a design that includes a capacitor recess and electrodes formed within the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If silicon capacitor is designed in IMD layers, then it can be manufactured using standard semiconductor process, but its height is limited by the number and thickness of IMD layers

Engineering Contradiction:
ImprovemanufacturabilityVSAvoidcapacitor height
Core Design Contradiction:
Ease of manufactureVSLength of stationary object

Solution Approach 1:

The capacitor structure transitions from being confined to horizontal IMD layers to extending vertically through the silicon substrate via TSV technology. The capacitor recess penetrates through the substrate, allowing the capacitor to achieve significant height (extending into the substrate) while maintaining compatibility with standard semiconductor manufacturing processes. This vertical dimensionality change resolves the height limitation imposed by finite IMD layer stacks.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If silicon capacitor is designed in silicon substrate, then it can achieve greater height and capacitance, but it will be influenced by high temperature environment in FEOL process

Engineering Contradiction:
Improvecapacitor heightVSAvoidhigh temperature influence
Core Design Contradiction:
Length of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The capacitor structure is designed and formed in the silicon substrate before the high-temperature FEOL processing steps. By establishing the capacitor recess, bottom electrode, and dielectric layer prior to FEOL, the capacitor components are protected from thermal damage during subsequent high-temperature processing. The TSV formation process is sequenced to complete capacitor fabrication before substrate exposure to FEOL temperatures.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If conventional capacitor is mounted on PCB, then it can be easily installed and replaced, but it occupies large area and cannot be made thin for high density applications

Engineering Contradiction:
Improveinstallation easeVSAvoidcapacitor area
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The capacitor is merged with the semiconductor substrate itself, forming an integrated structure where the capacitor recess, electrodes, and dielectric are fabricated as part of the substrate architecture. This integration eliminates the need for separate PCB mounting while achieving high density through vertical extension into the substrate. The TSV-based capacitor becomes an intrinsic part of the semiconductor device, providing both space savings and improved electrical performance.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12604488B2Silicon capacitor structure and method of manufacturing the same
Publication Date: 2026.04.14 POWERCHIP SEMICON MFG CORP
  • US12604488B2 patent drawing
  • US12604488B2 patent drawing
  • US12604488B2 patent drawing

AI summary

The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.