Silicon-Capped FinFET Fins for Oxidation-Free Isolation
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Solution Overview
Problem
Fin oxidation during the formation of isolation regions in fin field effect transistors (finFETs) leads to fin width loss, resulting in transistor performance degradation and yield loss, particularly in silicon-germanium fin structures.
Innovation Solution
A crystalline silicon capping layer is deposited on the top surfaces of fin structures to prevent oxidation during the formation of fin isolation regions, which is not sacrificial and becomes part of the transistor structure, with a controlled thickness of about 2 nm to ensure protection without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fin structures are formed without a capping layer, then the fabrication process is simpler, but fin oxidation occurs during isolation region formation leading to fin width loss
Solution Approach 1:
A crystalline silicon capping layer is deposited on the fin structures before the formation of isolation regions. This preliminary protective action prevents oxidation of the fin structures during subsequent processing steps, thereby maintaining fin width precision without complicating the overall fabrication process
Solution Approach 2:
The crystalline silicon capping layer serves as an intermediary protective layer between the fin structure and the oxidizing environment during isolation region formation. This mediator prevents direct contact between oxygen and the fin structure, eliminating fin width loss while adding minimal process complexity
2Reliability
If a thick capping layer is deposited to prevent oxidation, then fin protection is improved, but transistor performance degrades
Solution Approach 1:
The thickness of the crystalline silicon capping layer is precisely controlled within the range of 1-5 nm (optimally 2-3 nm). This parameter optimization provides sufficient protection against fin oxidation while maintaining transistor performance, resolving the contradiction between protection level and device functionality
3Device complexity
If no capping layer is used, then device complexity is reduced, but fin width loss occurs leading to yield loss
Solution Approach 1:
The crystalline silicon capping layer is deposited as a preliminary protective measure before isolation region formation. This simple preliminary step prevents fin width loss and associated yield reduction without significantly increasing device or process complexity
Solution Approach 2:
The thin crystalline silicon capping layer acts as an intermediary protective barrier that prevents oxidation-induced fin width loss during isolation formation. This mediator ensures high manufacturing yield by preserving fin dimensions while adding minimal structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The crystalline silicon capping layer effectively prevents fin oxidation, reducing defects and fin width loss, thereby enhancing transistor performance and manufacturing yield by relocating weak points away from the fin surfaces.
Implementation Method 1
a crystalline silicon layer is epitaxially grown on the fin structures formed on the semiconductor substrate
Data Source
AI summary
The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.