Silicon Carrier RDL Stack for Low-Cost 3D Die Integration
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Solution Overview
Problem
Existing semiconductor packaging technologies using interposers are costly, limiting their application to high-end markets, and silicon bridge technology is limited in 3D architectures and integration capabilities.
Innovation Solution
Incorporation of redistribution layers (RDLs) in a silicon carrier for lateral communication between circuit dies, eliminating the need for interposers or bridge dies, enabling heterogeneous integration with reduced costs and increased performance through wafer-level bonding and passive top carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used for heterogeneous integration, then communication bandwidth and performance are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts the essential function of lateral communication from the interposer structure and relocates it to the carrier substrate. By forming redistribution layers directly on the carrier, the design eliminates the need for a separate interposer component while maintaining the lateral signal routing capability, thereby reducing manufacturing cost without sacrificing communication bandwidth
Solution Approach 2:
The patent merges the carrier substrate and interposer functions into a single integrated structure. The carrier substrate simultaneously provides mechanical support and lateral communication pathways through integrated redistribution layers, combining what were previously separate components (carrier + interposer) into one unified structure that reduces overall system cost and complexity
2Ease of manufacture
If silicon bridge technology is used for lateral communication, then cost is reduced, but applicability to 3D architectures and integration capabilities are limited
Solution Approach 1:
The patent creates a universal carrier substrate design that can accommodate various 3D stacking architectures (wafer-on-wafer, chip-on-wafer, chip-on-chip) and different die size configurations. The redistribution layers on the carrier provide flexible lateral communication pathways that adapt to different architectural requirements, making the solution universally applicable across multiple 3D integration scenarios without requiring architecture-specific modifications
Solution Approach 2:
The patent transitions from the planar silicon bridge approach to a three-dimensional carrier substrate structure with vertically stacked dies and laterally extending redistribution layers. This dimensional change allows the carrier to provide both vertical support for stacked dies and lateral signal routing capabilities, enabling full 3D architecture applicability that the planar silicon bridge cannot achieve
3Productivity
If multiple dies are stacked in 3D configuration, then integration density and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-forming the redistribution layers on the carrier substrate before die stacking. This advance preparation of the lateral communication infrastructure on the carrier allows subsequent die attachment and TSV formation to proceed more efficiently, reducing overall manufacturing complexity despite the increased integration density achieved through 3D stacking
Data Source
AI summary
The disclosed semiconductor device can include a plurality of stacked circuit dies and a carrier attached to the plurality of stacked circuit dies. A plurality of redistribution layers in the carrier can provide lateral communication for one or more circuit dies of the plurality of stacked circuit dies. Various other methods, systems, and computer-readable media are also disclosed.