Silicon Chip Carrier Triangular Supports for Lower Thermal Conductance

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Solution Overview

Problem

Conventional methods for fabricating silicon chip carriers for pyroelectric IR detectors involve costly dry etching processes and increased lead times, with square or circular supports increasing contact area and thermal conductance, necessitating a more economical and efficient fabrication method.

Innovation Solution

A method utilizing solely wet bulk micromachining with anisotropic etchants to create triangular-shaped supports on both sides of a silicon wafer, minimizing contact area and enabling precise alignment for reduced thermal conductance and cost-effective production.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dry etching process is used for fabricating silicon chip carrier, then manufacturing precision is improved, but fabrication cost increases

Engineering Contradiction:

Improvechip carrier fabrication precisionVSAvoidfabrication cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention changes the etching parameter from dry etching to wet etching, specifically using anisotropic wet etchants like KOH or EDP. This parameter change maintains sufficient manufacturing precision for chip carrier fabrication while dramatically reducing fabrication costs, as wet etching is a more economical and established process in semiconductor manufacturing

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The invention adopts a disposable mask layer approach where a sacrificial layer (such as photoresist or silicon dioxide) is deposited, patterned, and then removed after etching. This cheap, temporary masking approach simplifies the process compared to expensive reusable masks, enabling cost-effective wet etching fabrication

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

2Manufacturing precision

If sequential wet and dry etching processes are used, then manufacturing precision is improved, but lead time increases

Engineering Contradiction:

Improvechip carrier fabrication precisionVSAvoidfabrication lead time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The invention merges the sequential wet and dry etching processes into a single anisotropic wet etching step. By using specifically oriented crystal planes and appropriate etchants, the process achieves the necessary precision in one operation, eliminating the need for sequential processing and significantly reducing fabrication lead time

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The invention performs preliminary crystal orientation selection by choosing silicon wafers with specific crystallographic orientations (such as <100> or <110>). This preliminary action enables the subsequent single-step anisotropic wet etching to automatically produce the required precise geometries without requiring multiple processing steps

Inventive Principle:

Principle #10Preliminary action

3Strength

If square or circular supports are used in chip carrier, then structural strength is improved, but thermal conductance increases

Engineering Contradiction:

Improvechip carrier structural strengthVSAvoidthermal conductance

Core Design Contradiction:

StrengthVSLoss of energy

Solution Approach 1:

The invention transitions from symmetric square or circular support shapes to asymmetric triangular-shaped supports. The triangular geometry with specific orientation relative to crystal planes reduces the contact area between the chip carrier and the pyroelectric element, thereby reducing thermal conductance while maintaining sufficient structural strength through optimized geometry

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The invention applies local quality optimization by specifically designing the support contact regions with triangular shapes that have reduced footprint. The support structures are locally optimized to provide minimal necessary mechanical support while maximizing thermal isolation, rather than using uniform large-area contacts

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method reduces thermal conductance and fabrication costs by using triangular-shaped supports fabricated through precise wet etching, allowing for efficient integration and lower thermal dissipation in miniaturized IR detectors.

Implementation Method 1

The present invention provides a method for fabricating silicon chip carriers using solely wet bulk micromachining... uses only a cost-effective anisotropic wet etchant for silicon bulk micromachining

Methodology Applied

Scientific EffectAnisotropic wet etching:

Data Source

PatentUS20250210388A1Method for fabricating silicon chip carriers using wet bulk micromachining for IR detector applications

Publication Date: 2025.06.26 COUNCIL OF SCI & IND RES

AI summary

The invented method is to realize a silicon chip carrier using wet bulk micromachining of silicon. In the silicon chip carrier, three (or more) supports are realized solely based on the wet etching of the silicon. The fabricated supports are triangular in shape and provide a minimum contact area between the sensing element and carrier. The invention provides a simple, cost-effective fabrication technology, which uses anisotropic wet etchant for silicon bulk-micromachining. A fabricated silicon wafer can be diced as per the requirement of single/multiple channel IR detectors. These chip carriers will cut down the IR detector cost with attractive lower thermal conductance in the field of gas sensors, spectrometry, thermal imaging, and fire detection.