On-Silicon Cavity Bridge for Fine-Pitch Die Interconnects
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Solution Overview
Problem
Current interconnection technologies for disaggregated semiconductor dies, such as EMIB and 3D die stacking, face limitations in fine line/space capability, increase Z-height, and are costly with complex designs, affecting load line and power delivery.
Innovation Solution
The use of an on-silicon cavity bridge substrate that is integrated into the dies, avoiding the need to remove copper layers from the package substrate, thus maintaining a direct Vccin feed path and preventing Z-height increase, while providing fine line/spacing dimensions through silicon processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EMIB bridge substrate is embedded into package substrate, then fine line/space interconnect capability is achieved, but copper layers must be removed which cuts Vccin feed-in power plane and degrades load line performance
Solution Approach 1:
The patent introduces an on-die cavity bridge as an intermediary structure that provides fine line/space interconnect capability without requiring removal of copper layers from the package substrate. The bridge substrate is positioned within cavities formed in the semiconductor dies themselves, acting as a mediator that achieves high-resolution interconnects while preserving the integrity of the power delivery network in the package substrate.
2Adaptability or versatility
If EMIB bridge substrate is embedded into package substrate, then interconnection of disaggregated dies is enabled, but number of package layers must be increased to maintain adequate performance
Solution Approach 1:
The patent moves the interconnection solution from the package substrate dimension to the on-die dimension by forming cavities within the semiconductor dies themselves. This dimensional shift allows the bridge substrate to be integrated within the die structure rather than requiring additional package layers, thereby enabling interconnection of disaggregated dies without increasing overall package complexity.
3Adaptability or versatility
If 3D die stacking architecture is used, then interconnection of disaggregated dies is achieved, but Z-height increases and design complexity increases
Solution Approach 1:
Instead of stacking dies vertically (3D architecture), the patent inverts the approach by placing bridge substrates horizontally within on-die cavities. This inversion of the interconnection paradigm enables disaggregated die interconnection in a lateral rather than vertical configuration, thereby achieving the desired adaptability without increasing Z-height.
4Manufacturing precision
If on-silicon cavity bridge substrate is used, then fine line/spacing dimensions are achieved through silicon processes, but additional manufacturing steps are required
Solution Approach 1:
The patent leverages the self-service capability of silicon fabrication processes to achieve fine line/spacing dimensions. By forming the bridge substrate from silicon and integrating it within on-die cavities using existing silicon process techniques, the manufacturing system serves itself to produce high-precision interconnects without requiring entirely new manufacturing capabilities.
Data Source
Figure 1A~1B
Figure 2A
Figure 2B~2C
AI summary
Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.