Silicon Channel Tempering for P-Type MBC Threshold Voltage Tuning
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Solution Overview
Problem
Conventional methods for forming p-type multi-bridge-channel (MBC) transistors face challenges in achieving satisfactory threshold voltages due to the difficulty in identifying suitable p-type work function metals and integrating silicon germanium channels, resulting in a small process window, less-than-ideal performance, and high fabrication costs.
Innovation Solution
A method involving the deposition of a germanium cladding layer on silicon channels, followed by annealing to convert it into a silicon germanium layer, and then subjecting it to a pre-clean process to form a germanium-containing interfacial layer, which provides dipoles or fixed charges, thereby lowering the threshold voltage for p-type MBC transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If more than one p-type work function metal layers are stacked over silicon channels to obtain desired threshold voltages, then the threshold voltage can be adjusted, but it is challenging to identify suitable p-type work function metals to achieve satisfactory band gap
Solution Approach 1:
The patent changes the material composition parameter by replacing conventional silicon channels with silicon germanium channels, where the germanium content can be adjusted to achieve desired threshold voltages. This parameter change approach allows continuous tuning of electrical properties without being constrained by discrete metal layer combinations.
Solution Approach 2:
The patent employs composite materials by creating silicon germanium channels that combine silicon and germanium in specific ratios. This composite approach enables simultaneous optimization of band gap, carrier concentration, and threshold voltage characteristics that cannot be achieved with pure silicon or conventional metal stacking alone.
2Manufacturing precision
If silicon channels in p-type devices are replaced with silicon germanium channels, then desired threshold voltages can be achieved, but integration of silicon germanium channels has proved challenging
Solution Approach 1:
The patent applies preliminary action by forming silicon germanium channels before other device structures are built. The channels are prepared in advance with controlled germanium content, and subsequent processing steps are designed to accommodate this pre-formed structure, simplifying overall integration.
Solution Approach 2:
The patent implements local quality by varying the germanium content in different regions of the channel to achieve spatially-dependent electrical properties. This allows different threshold voltages and carrier concentrations in different device regions without requiring different material systems throughout the entire device.
3Reliability
If conventional technologies for forming p-type MBC devices are used, then the intended purposes are generally adequate, but they are not satisfactory in all aspects including performance and fabrication costs
Solution Approach 1:
The patent employs a simpler, more cost-effective channel material system (silicon germanium) that can be integrated using existing semiconductor fabrication processes. This replaces complex multi-layer metal work function adjustments with a single material system that achieves the same electrical characteristics more economically.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the threshold voltage of p-type MBC transistors, improving their performance and reducing fabrication costs by utilizing a germanium-containing interfacial layer that creates desirable electrical properties.
Implementation Method 1
annealing to convert it into a silicon germanium layer
Implementation Method 2
provides dipoles or fixed charges, thereby lowering the threshold voltage
Data Source
AI summary
A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.