Silicon Chicklet Pedestal for Wafer-Level Probe Registration
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Solution Overview
Problem
Conventional ceramic pedestal substrates are expensive, have long lead times, and fail to maintain registration accuracy at tight wafer pitches less than 200 μm, making them unreliable for high-power and high-performance wafer-level tests.
Innovation Solution
A silicon chicklet pedestal with opposing faces and an array of vias, featuring insulating and conductive layers, and filled with conductive material, allowing for electrical connectivity between leads, is used in a wafer-level test probe, enabling precise registration at tighter pitches and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic pedestal substrates are used in wafer-level test probes, then structural support and electrical connectivity are provided, but manufacturing cost increases and lead time extends to 9-12 months
Solution Approach 1:
The patent replaces expensive ceramic pedestal substrates with a cost-effective silicon-based chicklet pedestal that can be rapidly manufactured. The silicon pedestal achieves the necessary structural and electrical functions at lower cost and shorter lead time, effectively substituting the traditional ceramic component with a more economical alternative that meets performance requirements for wafer-level testing.
Solution Approach 2:
The invention changes the material parameter from ceramic to silicon, which fundamentally alters the manufacturing characteristics. Silicon allows for faster fabrication processes and shorter lead times while maintaining the essential mechanical and electrical properties needed for probe card functionality in wafer-level testing applications.
2Reliability
If ceramic pedestal substrates are used, then electrical connectivity is achieved, but registration accuracy deteriorates at pitches less than 200 μm
Solution Approach 1:
The patent changes the substrate material parameter from ceramic to silicon, which enables superior registration accuracy at tighter pitches. Silicon's material properties allow for more precise metallurgy alignment and better footprint registration when testing wafers with pitches below 200 μm, while still providing reliable electrical connectivity through its conductive layers and via structures.
Solution Approach 2:
The silicon pedestal employs a composite structure combining silicon substrate with conductive and insulating layers. This composite approach allows optimization of both electrical connectivity and registration precision, as each layer can be engineered to fulfill specific functional requirements including signal transmission and dimensional stability at high precision.
3Ease of manufacture
If conventional ceramic processing is used, then pedestal fabrication is achieved, but capability to maintain registration accuracy at tighter pitch is lost
Solution Approach 1:
The invention changes the fabrication parameter by transitioning from ceramic processing to silicon-based manufacturing. Silicon processing techniques enable maintaining registration accuracy at tighter pitches through better material properties and more controllable fabrication processes, while still allowing for efficient pedestal fabrication through established semiconductor manufacturing methods.
4Manufacturing precision
If organic substrates are used instead of ceramic, then footprint registration accuracy improves at tighter pitch, but compatibility with conventional probe structures is reduced
Solution Approach 1:
The patent creates a composite silicon-based chicklet pedestal that combines the registration accuracy benefits of organic substrates with the structural and electrical compatibility of conventional ceramic probes. The multi-layer silicon structure with conductive and insulating layers provides both high precision footprint registration and full compatibility with existing probe card architectures and testing systems.
Data Source
AI summary
A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.