Silicon Core-Frame Packaging for Fine-Pitch Embedded Dies
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Solution Overview
Problem
Conventional semiconductor device packages face limitations in material structuring resolution and high costs due to the use of organic substrates and silicon interposers, which hinder device scaling and performance requirements.
Innovation Solution
The development of thin-form-factor semiconductor device packages using a core frame made of silicon with integrated vias and insulating layers, formed through micro-blasting or direct laser patterning, to enable fine feature formation and reduce thermal expansion mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If organic package substrates are used, then ease of manufacture and low cost are achieved, but material structuring resolution is insufficient for device scaling
Solution Approach 1:
The patent changes the material parameter from organic substrate to silicon-based core frame, enabling finer structuring resolution (e.g., 10 micrometer features) while maintaining manufacturability through specialized processes like micro-blasting and laser patterning
Solution Approach 2:
The patent replaces conventional mechanical structuring methods used for organic substrates with advanced techniques including micro-blasting, direct laser patterning, and chemical etching, which enable higher precision feature formation in silicon-based materials
2Reliability
If silicon interposers are used, then high-bandwidth density and lower-power communication are achieved, but manufacturing costs increase due to complex processes
Solution Approach 1:
The patent extracts the redistribution layer function from the substrate itself by forming conductive interconnections directly within the silicon core frame, eliminating the need for separate silicon interposer layers and reducing overall manufacturing complexity
Solution Approach 2:
The patent merges the substrate and redistribution layer functions into a single silicon-based core frame structure, where conductive interconnections are formed directly within the substrate material, simplifying the overall package architecture and reducing manufacturing steps
3Manufacturing precision
If device scaling is increased, then circuit density is improved, but thermal expansion mismatch and mechanical defects increase
Solution Approach 1:
The patent uses a homogeneous silicon-based material for the core frame that provides uniform thermal and mechanical properties throughout the structure, reducing thermal expansion mismatch and associated mechanical defects during device scaling
Solution Approach 2:
The patent employs composite material structures including silicon-based core frame with integrated insulating layers and conductive interconnections, creating a multi-material system that manages thermal expansion and mechanical stress more effectively than single-material approaches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved scalability, reduced mechanical defects, and lower costs by enabling fine feature patterning and minimizing thermal expansion issues, enhancing die-to-package area ratios and through-package bandwidth.
Implementation Method 1
minimizing thermal expansion issues
Implementation Method 2
An insulating layer is disposed over the first surface and the second surface, the insulating layer contacting at least a portion of each side of the semiconductor die, and an electrical interconnection disposed within the via, wherein the insulating layer is disposed between the via surface and the electrical interconnection
Data Source
AI summary
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.