Silicon Core Package Assembly for High-Density Interconnects
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Solution Overview
Problem
Conventional semiconductor package and PCB assemblies face limitations in scalability and performance due to material rigidity, planarity issues, and coefficient of thermal expansion mismatches, leading to low electrical bandwidths and increased manufacturing costs, especially with the use of organic substrates and silicon interposers.
Innovation Solution
The development of a semiconductor device assembly featuring a silicon core structure with a passivating thermal oxide layer, a dielectric layer made of epoxy resin with silica particles, and redistribution layers formed on the dielectric layer, which includes an adhesion layer and a copper layer, enabling thin-form-factor and high-density interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon interposers are used for high-density interconnections, then electrical bandwidth and integration density are improved, but manufacturing cost and process complexity increase due to high-aspect-ratio via etching and chemical mechanical planarization
Solution Approach 1:
The patent changes the via aspect ratio parameter by using shallow vias (5-10 μm depth) instead of deep TSVs (100+ μm depth), and uses spin-on glass (SOG) material with different mechanical properties than silicon. This allows formation of interconnections without requiring high-aspect-ratio etching and CMP processes, thereby reducing manufacturing complexity while maintaining high integration density
Solution Approach 2:
The patent uses spin-on glass (SOG) as a temporary sacrificial material that is easily removed after serving its purpose of defining via locations and providing structural support during processing. This disposable approach eliminates the need for permanent silicon interposer structures and complex planarization processes
2Ease of manufacture
If conventional organic package substrates are used, then manufacturing cost is reduced, but material structuring resolution is insufficient to sustain device scaling and performance requirements
Solution Approach 1:
The patent creates a composite structure combining organic package substrate with spin-on glass layers and metal interconnections. The SOG layer provides the necessary structural precision and planarity for high-resolution patterning, while the organic substrate maintains low manufacturing cost. This composite approach achieves both affordability and high manufacturing precision
Solution Approach 2:
The spin-on glass acts as an intermediary layer between the organic package substrate and the metal interconnections. It provides a planar, structurable surface that enables precise feature formation, while being easily removable after serving its mediating function. This intermediary allows conventional low-cost substrates to achieve high-precision features
3Reliability
If through-silicon vias are formed in silicon interposers, then high-bandwidth density and lower-power chip-to-chip communication are achieved, but formation costs increase due to high-aspect-ratio etching and chemical mechanical planarization
Solution Approach 1:
The patent fundamentally changes the via depth parameter from deep TSVs (100+ μm) to shallow vias (5-10 μm) in spin-on glass, and changes the material from silicon to SOG. These parameter changes enable via formation using simple photolithography and etching processes without requiring expensive high-aspect-ratio etching equipment and CMP facilities, thereby achieving high bandwidth density at lower formation cost
Solution Approach 2:
The patent replaces the mechanical planarization process (CMP) with a chemical dissolution approach where spin-on glass is selectively removed using hot phosphoric acid or oxygen plasma. This substitution eliminates the need for complex mechanical planarization equipment and processes, reducing manufacturing cost while achieving the necessary planarity for high-density interconnections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances electrical performance by reducing capacitive coupling and leakage current, improving thermal management, and allowing for higher device densities and power efficiency while reducing manufacturing costs through precise patterning and flexible solder ball distribution.
Implementation Method 1
a passivating layer surrounding the silicon structure and including a thermal oxide
Implementation Method 2
a dielectric layer surrounding the passivating layer and formed of an epoxy resin having silica particles disposed therein
Implementation Method 3
an adhesion layer formed on the dielectric layer and formed of molybdenum, a copper seed layer formed on the adhesion layer, and a copper layer formed on the copper seed layer
Data Source
AI summary
The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.