Silicon Dioxide Double Liner for Pattern Density Uniformity
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Solution Overview
Problem
The fabrication of advanced integrated circuits faces challenges in achieving uniformity of silicon oxide layers, particularly in high-k metal gate electrode structures and strain-inducing semiconductor alloys, which leads to increased leakage currents and variations in transistor performance due to dependencies on pattern density and differences in dielectric cap layer thickness.
Innovation Solution
A silicon dioxide double liner is used, comprising an undoped silicon dioxide layer and a hydrogen-containing silicon dioxide layer, deposited using high density plasma CVD, to reduce pattern density dependency and achieve superior uniformity and gap filling capabilities, thereby stabilizing the dielectric cap material and spacer elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin silicon dioxide layer is deposited to provide required gate capacitance, then capacitive coupling between gate and channel is improved, but leakage current increases due to direct tunneling
Solution Approach 1:
The patent applies a composite gate dielectric structure consisting of multiple layers: a first silicon oxide layer (3-7 nm thick) providing tunnel barrier function, a second dielectric layer (5-15 nm thick) with higher dielectric constant providing capacitance, and a third silicon oxide layer (1-3 nm thick) providing additional tunnel barrier. This composite structure achieves the required capacitive coupling while preventing excessive leakage current by distributing the electrical function across multiple material layers with complementary properties.
Solution Approach 2:
The patent applies different material compositions and thicknesses at different positions within the gate dielectric stack. The silicon oxide layers are positioned at the interfaces with the channel and gate electrode where tunnel barrier properties are critical, while the high-k dielectric layer is positioned in the middle where capacitance is most needed. This local differentiation of material quality optimizes both capacitance and leakage prevention.
2Speed
If silicon dioxide layer thickness is reduced to improve switching speed, then channel inversion capability is enhanced, but uniformity across substrate deteriorates
Solution Approach 1:
The patent divides the gate dielectric into multiple separate layers deposited in sequential steps, each with optimized thickness and material composition. The first silicon oxide layer (3-7 nm), second dielectric layer (5-15 nm), and third silicon oxide layer (1-3 nm) are deposited independently, allowing each layer to be optimized for its specific function while collectively achieving the required switching performance and uniformity across the substrate.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing a high-k dielectric material in the second layer, and adjusts the thickness parameters of each layer to achieve optimal electrical characteristics. By varying the thickness of each individual layer and the dielectric constant of the middle layer, the patent achieves both fast switching speed and improved uniformity across the substrate.
3Manufacturing precision
If complex deposition processes are used to achieve uniform oxide layers, then across-substrate uniformity is improved, but process complexity increases
Solution Approach 1:
The patent uses silicon oxide (SiO2) as the material for the first and third layers, which provides homogeneous chemical composition and similar deposition characteristics. This homogeneity simplifies the deposition process compared to using entirely different materials, as the same or similar deposition techniques can be used for both silicon oxide layers, reducing process complexity while maintaining excellent uniformity across the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced yield losses and improved transistor characteristics by ensuring uniformity across the substrate and die, enhancing the performance and reliability of semiconductor devices, especially in highly scaled semiconductor devices.
Implementation Method 1
depositing a second silicon dioxide layer on the first silicon dioxide layer by performing a high density plasma chemical vapor deposition process
Implementation Method 2
performing a high density plasma chemical vapor deposition process
Data Source
AI summary
A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.