Silicon Dioxide-Polysilicon Stack Etching with Pulsed RF Plasma

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Solution Overview

Problem

Current semiconductor manufacturing techniques face challenges in etching multi-layered stacks of silicon and dielectric layers, particularly in 3D NAND architecture, due to compositional differences between polysilicon and silicon dioxide, which most plasma etch systems are not designed to handle effectively, leading to difficulties in achieving high selectivity and aspect ratios.

Innovation Solution

A method employing a plasma etch chamber with non-corrosive process gases such as SF6 and NF3, energized by pulsed RF energy, to etch both silicon and dielectric layers with high selectivity and aspect ratios, avoiding the use of corrosive gases like HBr or Cl2, and utilizing a mask layer with RF pulsing to maintain high selectivity and prevent etch stop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional plasma etch systems use corrosive gases like HBr or Cl2, then silicon etching performance is improved, but mask layer selectivity deteriorates and etch stop occurs

Engineering Contradiction:
Improveetching precisionVSAvoidmask layer selectivity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the chemical composition parameters of the etchant from corrosive gases (HBr, Cl2) to non-corrosive fluorocarbon-based gases. This parameter change enables simultaneous achievement of high etching precision for silicon and high mask layer selectivity, as the non-corrosive nature prevents unwanted mask erosion while maintaining effective silicon etching through fluorocarbon chemistry

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a two-step etching approach where a first etchant creates initial openings and a second etchant completes the through-etch. This copying approach allows each etchant to be optimized for its specific function, with the second non-corrosive etchant replicating and completing the pattern initiated by the first etchant while providing superior mask selectivity

Inventive Principle:
Principle #26Copying

2Manufacturing precision

If plasma etch systems are designed for high dielectric layer etching, then silicon dioxide etching selectivity is improved, but polysilicon etching capability deteriorates

Engineering Contradiction:
Improvedielectric layer etching selectivityVSAvoidmulti-material etching capability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent makes the plasma etch system universal by enabling it to effectively etch both silicon dioxide and polysilicon using the same non-corrosive fluorocarbon-based etchant. This multi-functionality is achieved through the unique chemistry of fluorocarbon gases that can attack both dielectric and semiconductor materials while maintaining high selectivity to the mask layer

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the etching process into multiple steps using different etchants, with the second etchant being a non-corrosive fluorocarbon-based gas specifically optimized for etching both silicon and silicon dioxide with high mask selectivity. This segmentation allows each step to address specific material removal requirements

Inventive Principle:
Principle #1Segmentation

3Device complexity

If single-step etching is used for multi-layered stacks, then process complexity is reduced, but etching uniformity and selectivity deteriorate

Engineering Contradiction:
Improveetching process complexityVSAvoidetching uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the etching of multi-layered stacks into multiple sequential steps, each using a specific etchant optimized for particular layers. The first etchant addresses initial openings and the second non-corrosive etchant completes the through-etch with high uniformity and selectivity, ensuring precise control over each layer removal while maintaining overall process manageability

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient etching of silicon and dielectric layers with high aspect ratios, achieving selectivity greater than 1:1 and allowing for the formation of 3D NAND memory devices with precise feature creation, such as vias and trenches, without the need for multiple etch systems or recipes.

Implementation Method 1

introducing process gases into the chamber. The process gases are all non-corrosive. The method involves energizing the process gases into a plasma with RF energy of at least one frequency

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

The RF energy is pulsed over time between an RF on state and an RF off state

Methodology Applied
Scientific EffectRF energy: Electromagnetic Induction

Data Source

PatentUS10643854B2Silicon dioxide-polysilicon multi-layered stack etching with plasma etch chamber employing non-corrosive etchants
Publication Date: 2020.05.05 APPLIED MATERIALS INC
  • US10643854B2 patent drawing
  • US10643854B2 patent drawing
  • US10643854B2 patent drawing

AI summary

Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF6 and/or NF3 typically only suitable for dielectric layers, are energized by pulsed RF to achieve high aspect ratio etching of silicon/silicon dioxide bi-layers stacks without the addition of corrosive gases, such as HBr or Cl2. In embodiments, a mask open etch and the multi-layered stack etch are performed in a same plasma processing chamber enabling a single chamber, single recipe solution for patterning such multi-layered stacks. In embodiments, 3D NAND memory cells are fabricated with memory plug and/or word line separation etches employing a fluorine-based, pulsed-RF plasma etch.