Silicon Epitaxial Layer for Vertical Semiconductor Stacking
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Solution Overview
Problem
Existing semiconductor device stacking technologies face challenges in bonding substrates and forming via holes and electrodes due to limitations in grinding and electrical interconnection, leading to difficulties in vertically integrating multiple chips effectively.
Innovation Solution
The method involves forming a silicon epitaxial layer on a first semiconductor device, creating connection vias through this layer to electrically interconnect with a second device, which is mounted on top, eliminating the need for additional bonding and enhancing the bonding strength and via electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a first semiconductor substrate and a second semiconductor substrate are bonded together using an adhesive to vertically stack chips, then the devices can be integrated into a single package, but the bonding strength is insufficient and additional bonding processes are required
Solution Approach 1:
A silicon epitaxial layer is introduced as an intermediary between the first semiconductor substrate and the second semiconductor substrate. This epitaxial layer serves as a bonding interface that eliminates the need for adhesive bonding, providing strong mechanical and electrical connection between the stacked chips while simplifying the overall bonding process
Solution Approach 2:
The invention changes the physical and chemical parameters of the bonding interface by using a silicon epitaxial layer with specific crystal structure and material properties. This allows for direct bonding without adhesives, improving bonding strength and eliminating complex bonding process steps
2Reliability
If via holes and via electrodes are formed through ground substrates to electrically interconnect stacked chips, then electrical connection is achieved, but the process is difficult due to grinding technology limitations
Solution Approach 1:
The silicon epitaxial layer is formed in advance on the first semiconductor substrate before the second chip is stacked. Connection vias are then formed through this pre-prepared epitaxial layer, which simplifies the via formation process compared to grinding through the entire substrate thickness and improves electrical interconnection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient vertical stacking of multiple devices into a single package, reducing the complexity and limitations of existing methods by providing strong electrical connections and minimizing the need for additional bonding processes, thus facilitating compact semiconductor device integration.
Implementation Method 1
forming a silicon epitaxial layer on a first semiconductor device
Data Source
AI summary
Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via.