Silicon Epitaxial Substrate Stacking Fault Suppression
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Solution Overview
Problem
The occurrence of stacking faults in epitaxial layers is caused by phosphorus and silicon precipitates (Si—P defects) formed during the crystal growth process, which are difficult to inhibit, leading to residual strains in the crystal structure.
Innovation Solution
A method of manufacturing silicon epitaxial substrates that involves growing a silicon single crystal by the Czochralski method with phosphorus doping, monitoring the cooling passage time, and performing a low-temperature holding step in the epitaxial growth furnace to dissolve and escape phosphorus from Si—P precipitates, thereby reducing residual strains and suppressing stacking faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phosphorus is added at high concentration during single crystal ingot growth to achieve low electrical resistivity, then the electrical resistivity of the substrate is lowered, but a large number of stacking faults occur in the epitaxial layer
Solution Approach 1:
The patent applies preliminary action by performing a pre-treatment step before epitaxial growth where the silicon single crystal is heated to 700-1000°C for 1-10 minutes to dissolve Si-P precipitates formed during crystal growth. This preliminary thermal treatment eliminates the harmful precipitates before the epitaxial layer is grown, preventing stacking faults while maintaining the low electrical resistivity achieved through high phosphorus concentration doping.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the heating temperature and time parameters during the pre-treatment process. The temperature is set to 700-1000°C and time to 1-10 minutes, which are optimized parameters to effectively dissolve Si-P precipitates without causing excessive phosphorus loss or other defects. This parameter optimization allows the process to resolve the contradiction between achieving low resistivity and preventing stacking faults.
2Reliability
If phosphorus is added at high concentration during single crystal ingot growth, then the electrical resistivity is lowered, but Si-P defects are formed during the crystal growth process
Solution Approach 1:
The patent converts the harmful Si-P defects into a beneficial process by utilizing the same heating treatment that dissolves the harmful precipitates. The heating to 700-1000°C for 1-10 minutes serves dual purposes: it dissolves the harmful Si-P precipitates while also ensuring proper phosphorus distribution and maintaining crystal structure integrity. This transforms the problematic defect formation into a controlled, beneficial thermal processing step.
Solution Approach 2:
The patent applies preliminary action by performing a pre-treatment step before epitaxial growth where the silicon single crystal is heated to 700-1000°C for 1-10 minutes to dissolve Si-P precipitates formed during crystal growth. This preliminary thermal treatment eliminates the harmful precipitates before the epitaxial layer is grown, preventing stacking faults while maintaining the low electrical resistivity achieved through high phosphorus concentration doping.
3Productivity
If the cooling process is accelerated during single crystal growth, then the production time is reduced, but the number of stacking faults increases
Solution Approach 1:
The patent applies preliminary action by performing a pre-treatment step before epitaxial growth where the silicon single crystal is heated to 700-1000°C for 1-10 minutes to dissolve Si-P precipitates formed during crystal growth. This preliminary thermal treatment eliminates the harmful precipitates before the epitaxial layer is grown, preventing stacking faults while maintaining the low electrical resistivity achieved through high phosphorus concentration doping.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the heating temperature and time parameters during the pre-treatment process. The temperature is set to 700-1000°C and time to 1-10 minutes, which are optimized parameters to effectively dissolve Si-P precipitates without causing excessive phosphorus loss or other defects. This parameter optimization allows the process to resolve the contradiction between achieving low resistivity and preventing stacking faults.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the occurrence of stacking faults by continuously dissolving and escaping phosphorus from Si—P precipitates, resulting in a silicon epitaxial substrate with improved crystal structure stability.
Implementation Method 1
adding phosphorus as a dopant, a step of monitoring the passage time from 700° C. to 600° C. when the silicon single crystal is cooled
Implementation Method 2
holding at low temperature of the epitaxial growth furnace for 120 s to 300 s at a temperature of 750° C. or more and 900° C. or less when the passage time is less than 300 min at 700° C. to 600° C., or at a temperature of 900° C. or more and 1000° C. or less when the passage time is 300 min or more at the above temperature range
Implementation Method 3
the dissolution of the phosphorus contained in the Si—P precipitates into the surroundings and the escape of the dissolved phosphorus from the substrate occur simultaneously
Data Source
AI summary
The disclosed silicon epitaxial substrate production method and silicon epitaxial substrate prevent the occurrence of stacking fault. The method includes growing a silicon single crystal to which phosphorus is added as a dopant and of which the electrical resistivity is adjusted to 0.6 to 1.0 mΩ·cm using the Czochralski method. The silicon single crystal is monitored for a 700-600° C. passage time during cooling. The silicon single crystal is sliced and the sliced product is placed in an epitaxial growth furnace. The method further includes retaining the furnace temperature of the epitaxial growth furnace for 120 seconds to 300 seconds at a temperature ranging from 750° C. to 900° C. inclusive when the 700-600° C. passage time is less than 300 minutes and at a temperature ranging from 900° C. to 1000° C. inclusive when the 700-600° C. passage time is 300 minutes or more. Epitaxial growth is performed following the retention step.