Silicon Epitaxial Wafer Growth Conditions for Low DIC Defects
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Solution Overview
Problem
Silicon epitaxial wafers with a {110} plane surface often exhibit irregularly shaped microscopic step defects, leading to high DIC defects that are difficult to detect and affect device performance.
Innovation Solution
A method for producing silicon epitaxial wafers by growing an epitaxial layer on a silicon single crystal wafer with a {110} plane or an off-angle less than 1 degree from it, at a temperature of 1100° C. to 1135° C. and a growth rate of 2.0 μm/min to 3.0 μm/min, followed by mirror-polishing with abrasive grains of 20 nm or less, to reduce DIC defects and surface roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an epitaxial layer is grown on a {110} plane silicon wafer to achieve high carrier mobility, then device performance is improved, but microscopic step defects occur on the surface leading to high DIC defects
Solution Approach 1:
The patent applies parameter changes by precisely controlling the growth temperature (1100-1135°C) and growth rate (2.0-3.0 μm/min) during vapor phase epitaxial growth. This specific parameter range resolves the contradiction by enabling high-quality epitaxial layer formation on {110} plane wafers while suppressing the formation of microscopic step defects that cause DIC defects
Solution Approach 2:
The patent employs preliminary action through mirror polishing of the silicon wafer surface before epitaxial growth. By pre-polishing the substrate to high flatness standards, the foundation is prepared to prevent the formation of microscopic step defects during subsequent epitaxial growth, thereby reducing DIC defects while maintaining the benefits of {110} plane high mobility
2Productivity
If conventional epitaxial growth conditions are used, then production efficiency is maintained, but DIC defects increase due to microscopic step defects
Solution Approach 1:
The patent optimizes growth parameters within a specific range (temperature: 1100-1135°C, growth rate: 2.0-3.0 μm/min) that simultaneously achieves high production efficiency and low DIC defects. This parameter optimization allows maintaining productive growth rates while preventing defect formation, resolving the contradiction between productivity and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively suppresses DIC defects to 1.5 counts/300 mm wafer or less and reduces surface roughness to less than 10 nm, improving wafer quality and device characteristics.
Implementation Method 1
an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer
Implementation Method 2
the mirror polishing is preferably performed with a polishing margin of more than 0 μm and 0.2 μm or less using a polishing liquid that contains abrasive grains having a grain diameter of 20 nm or less
Data Source
AI summary
To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C. and growing the epitaxial layer in the vapor phase at a growth rate of 2.0 μm/min to 3.0 μm/min.