Silicon Epitaxial Wafer Surface Roughness Control
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Solution Overview
Problem
Silicon epitaxial wafers with a {110} surface orientation often exhibit periodic stripe-like irregularities and surface roughening due to facet structure formation, leading to defective semiconductor devices, as existing manufacturing methods fail to adequately reduce these irregularities.
Innovation Solution
A manufacturing method involving rapid cooling of the silicon wafer at a rate greater than 500°C/minute between 750°C and 650°C, or using a passivation film formed at 720°C or more to prevent silicon atom migration, and misorienting the wafer surface by 3.0° to 6.2° to suppress facet structure formation, combined with annealing to form ordered monolayer step structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a silicon epitaxial wafer is manufactured using a single crystal substrate with a main surface of {110}, then the wafer can be used for special MPUs and semiconductor pressure sensors, but periodic stripe-like irregularities and surface roughening occur due to facet structure formation
Solution Approach 1:
The patent applies parameter changes by modifying the cooling rate parameter during epitaxial growth. Specifically, it uses a rapid cooling rate of more than 500°C per minute in the temperature range of 750°C to 650°C to suppress silicon atom migration and prevent facet structure formation, thereby reducing surface roughness while maintaining {110} orientation suitability for special applications
2Ease of manufacture
If conventional epitaxial growth is performed on a silicon single crystal substrate with surface orientation of (110), then the growth process can be standardized, but surface irregularities of several nanometers to several dozens of micrometers are formed
Solution Approach 1:
The patent modifies the cooling rate parameter from conventional slow cooling to rapid cooling (>500°C/min) during the epitaxial growth process. This parameter change suppresses silicon atom migration on the (110) surface, preventing the formation of large surface irregularities while maintaining process standardization for manufacturing silicon epitaxial wafers
3Ease of operation
If the cooling rate is slow during epitaxial growth, then the growth process is stable and easy to control, but silicon atom migration occurs leading to facet structure formation and surface roughening
Solution Approach 1:
The patent changes the cooling rate parameter to more than 500°C per minute during the temperature range of 750°C to 650°C. This rapid cooling suppresses silicon atom migration that causes facet formation, improving surface quality while the process remains controllable through precise temperature management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces surface irregularities and roughness, preventing facet structure formation and resulting in a high-quality silicon epitaxial wafer with reduced defects and improved visual appearance.
Implementation Method 1
In the cooling step, a rapid cooling at a cooling rate of more than 500° C./minute is performed in a range of 750° C. to 650° C.
Implementation Method 2
a passivation film is grown on a main surface of the epitaxial layer at a temperature of 720° C. or more
Implementation Method 3
combined with annealing to form ordered monolayer step structures
Data Source
AI summary
This method for manufacturing a silicon epitaxial wafer includes: a step of growing an epitaxial layer having silicon on a silicon wafer having a main surface of {110}; and a cooling step of cooling the silicon wafer after growing the epitaxial layer. In a first aspect, in the cooling step, a rapid cooling at a cooling rate of more than 500° C./minute is performed in a range of 750° C. to 650° C. In a second aspect, in the cooling step, a passivation film is grown on a main surface of the epitaxial layer at a temperature of 720° C. or more. In a third aspect, a single crystal silicon wafer in which a misorientation angle of a main surface of {110} surface is in a range from 3.0° to 6.2° inclined towards a <110> direction perpendicular to the main surface or a <111> direction is used as the silicon wafer.