Dual-Side Silicon Etching with Metallic Passivation
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Solution Overview
Problem
Current anisotropic deep silicon etching techniques face challenges such as structural instability, unwanted etching, and difficulty in balancing etch rates for features with varying aspect ratios, leading to inefficiencies and increased production costs in forming chip-scale cooling devices for semiconductor devices.
Innovation Solution
The method involves etching features from both sides of a silicon wafer using a mask layer with a lower etch rate, coating surfaces with a passivation layer to prevent unwanted etching, and controlling etch rates to achieve precise feature dimensions, thereby reducing lateral etch creep and mask layer thickness, which enhances precision and reduces production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic deep silicon etching is used to form features, then features with high aspect ratios can be achieved, but structural instability and unwanted etching occur
Solution Approach 1:
The etching process is segmented into multiple sequential steps: first etching from the top surface to a first depth plane, then coating with metallic coating, then etching from the bottom surface to a second depth plane. This segmentation allows better control over feature formation and reduces unwanted lateral etching, improving both precision and structural stability.
Solution Approach 2:
The top surface features are etched and coated with metallic coating before bottom surface etching begins. This preliminary action protects the top features during subsequent bottom etching and allows precise control over feature dimensions before final through-etching occurs.
2Manufacturing precision
If mask layer thickness is increased to prevent unwanted etching, then etching precision is improved, but manufacturing complexity and production time increase
Solution Approach 1:
The process uses a mask layer with a lower etch rate than the silicon wafer, and controls etching through multiple depth planes with intermediate metallic coating. This parameter-based control achieves precise etching without requiring excessively thick mask layers, maintaining both precision and productivity.
Solution Approach 2:
The etching process is divided into sequential steps with intermediate metallic coating application. This segmentation allows precise control over feature dimensions at each stage without requiring a single thick mask layer, reducing overall manufacturing time while maintaining precision.
3Productivity
If features with varying aspect ratios are etched simultaneously, then production time is reduced, but difficulty in balancing etch rates increases
Solution Approach 1:
The etching of features with varying aspect ratios is segmented into sequential steps: top surface etching to first depth plane, metallic coating application, then bottom surface etching to second depth plane. This allows different etch rates to be optimized for different feature types at different stages, maintaining precision while improving overall productivity.
Solution Approach 2:
Top surface features are etched and coated with metallic coating before bottom surface etching. This preliminary action allows optimization of etch parameters for top features first, then adjustment for bottom features, achieving balanced etch rates for varying aspect ratios while maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise and efficient etching of features with reduced lateral etch creep and mask layer thickness, improving the structural integrity and functionality of chip-scale cooling devices while decreasing production time and costs.
Implementation Method 1
coating the top surface and the one or more top surface features with a metallic coating
Data Source
AI summary
A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.