(111) Silicon Facet Capping Layer for pMOS
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Solution Overview
Problem
The challenge in manufacturing ultra-small size semiconductor devices is the generation of pitting defects and thermal budget issues due to the use of hydrogen chloride in forming silicon capping layers, which affects the hole mobility and operating speed of p-channel MOS transistors.
Innovation Solution
A method involving the formation of a silicon capping layer with an (111) inclined face using an etching solution with a slower etching rate for the (111) face, such as ammonium hydroxide or tetramethylammonium hydroxide, without high-temperature heat treatment, to create a SiGe mixed crystal layer that increases hole mobility without generating pitting defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hydrogen chloride is used to form silicon capping layers, then the capping layer can be formed, but pitting defects are generated and thermal budget issues occur
Solution Approach 1:
The patent extracts and removes hydrogen chloride from the capping layer formation process, replacing it with alternative materials or methods that do not cause pitting defects. This eliminates the harmful extraction of silicon atoms by HCl while maintaining the protective function of the capping layer.
Solution Approach 2:
The patent changes the chemical composition parameters of the capping layer formation process by substituting hydrogen chloride with other chemicals or physical deposition methods. This parameter change eliminates the pitting defect mechanism while preserving the capping layer's protective function.
2Manufacturing precision
If high-temperature heat treatment is applied, then the silicon capping layer can be formed, but thermal budget issues and defects occur
Solution Approach 1:
The patent replaces the thermal field (high-temperature heat treatment) with alternative methods such as chemical vapor deposition, atomic layer deposition, or low-temperature annealing processes. This substitution achieves the desired crystalline structure without exceeding the thermal budget constraints.
Solution Approach 2:
The patent changes the temperature parameter from high-temperature processing to low-temperature or room-temperature processes, while adjusting other parameters such as pressure, gas flow, or deposition rate to achieve the desired capping layer quality without thermal damage.
3Productivity
If the etching rate for (111) face is increased, then the etching process is faster, but the selectivity and precision of facet formation is reduced
Solution Approach 1:
The patent applies local quality by using etching solutions that exhibit different etching rates for different crystallographic orientations. The (111) face is selectively etched at a controlled rate while other faces are etched at different rates, creating the desired facet geometry with high precision. This is achieved through anisotropic etching where the etchant chemistry interacts differently with various crystal planes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the hole mobility and operating speed of semiconductor devices by minimizing pitting defects and thermal issues, resulting in improved electric properties without the need for high-temperature processes.
Implementation Method 1
A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet (Si facet) having an (111) inclined face
Implementation Method 2
since the SiGe mixed crystal layers 1A and 1B may have a larger lattice constant than that of the silicon substrate 1, a compressive stress may be formed as designated by an arrow 'a' in the SiGe mixed crystal layers 1A and 1B
Implementation Method 3
Since the SiGe mixed crystal layers 1A and 1B may be formed through an epitaxial growing process from the silicon substrate 1
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.