Silicon-Filled Opening Void Reduction via Amorphous Deposition and Annealing

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Solution Overview

Problem

Semiconductor devices often form voids or seams in silicon-filled openings due to non-uniform deposition processes, which can adversely impact electronic device performance.

Innovation Solution

A method involving the deposition of an amorphous silicon film into substrate openings, followed by exposure to a silicon mobility inhibitor and subsequent annealing, which reduces or eliminates voids while maintaining the surface smoothness and converting the amorphous silicon to a more crystalline form.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If silicon is deposited to fill the opening from the sides and bottom, then the opening can be completely filled, but non-uniform growth causes voids and seams to form in the interior

Engineering Contradiction:
Improvefill uniformityVSAvoidvoid formation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the deposition temperature parameter to below 550°C to deposit amorphous silicon instead of crystalline silicon. This parameter change allows for more uniform deposition behavior and reduces the formation of voids and seams during the filling process, as amorphous silicon exhibits different growth characteristics compared to crystalline silicon.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes the phase transition of silicon from amorphous to crystalline state through controlled annealing. The silicon is first deposited in amorphous phase at low temperature to ensure uniform filling, then subsequently annealed to convert it to the desired crystalline phase, thereby avoiding void formation during deposition while achieving the required material properties.

Inventive Principle:
Principle #36Phase transitions

2Productivity

If the top of the opening closes up first due to higher deposition rate, then filling is completed faster, but voids are trapped in the interior

Engineering Contradiction:
Improvefilling speedVSAvoidvoid elimination
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By changing the deposition temperature to below 550°C, the patent modifies the deposition kinetics to produce amorphous silicon with more uniform growth rates throughout the opening. This prevents the top surface from closing up prematurely and trapping voids, while still maintaining efficient filling speeds.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If amorphous silicon is deposited at low temperature, then uniform filling is achieved, but the silicon must be subsequently annealed to convert to polysilicon

Engineering Contradiction:
Improvedeposition uniformityVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent intentionally deposits silicon in the amorphous phase at low temperature to achieve uniform filling, then employs a controlled annealing process to transition the material to the desired polysilicon phase. This two-step approach separates the uniformity achievement (deposition) from the phase requirement (annealing), optimizing each step independently.

Inventive Principle:
Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces or eliminates voids in silicon-filled openings, ensuring a smooth surface and crystallization of the silicon, making the silicon fill suitable for integrated circuit structures without causing surface roughening.

Implementation Method 1

The deposited amorphous silicon film is exposed to an oxidizing gas, a nitriding gas, or an n-type dopant gas at a temperature of about 575° C. or below

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

The deposited amorphous silicon film is exposed to an oxidizing gas, a nitriding gas, or an n-type dopant gas at a temperature of about 575° C. or below

Methodology Applied
Scientific EffectNitriding: Nitriding

Implementation Method 3

The substrate is subsequently heated to an anneal temperature. The substrate is then maintained at the anneal temperature to crystallize the amorphous silicon film in the trench. This anneal may convert the amorphous silicon film to a polysilicon film

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 4

The substrate is then maintained at the anneal temperature to crystallize the amorphous silicon film in the trench

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS9837271B2Process for forming silicon-filled openings with a reduced occurrence of voids
Publication Date: 2017.12.05 ASM IP HLDG BV
  • US9837271B2 patent drawing
  • US9837271B2 patent drawing
  • US9837271B2 patent drawing

AI summary

In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.