Silicon Fin Sidewall Slope Control for Broader Conductive Trenches
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Solution Overview
Problem
The challenge in electronic device design and fabrication lies in creating densely packed, small-scale structures that maintain performance characteristics such as low refresh time, low write recovery time, and low row hammer characteristics without sacrificing device performance, particularly in memory devices where conductive features like word lines need to exhibit low electrical resistance.
Innovation Solution
The solution involves forming relatively broad openings adjacent to narrow silicon structures using a low bias, isotropic etching act following a high bias, anisotropic etching act, which narrows the silicon structures and broadens the openings, allowing for greater conductive material volume and improved control, reducing row hammer characteristics and write recovery time while maintaining the structural integrity and performance of the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high bias, anisotropic etching is used to form narrow silicon structures, then manufacturing precision of fin width is improved, but the opening width remains limited and conductive material volume is insufficient
Solution Approach 1:
The etching process is segmented into two distinct stages: first a high bias anisotropic etch to define the fin structure with precise width control, then a low bias isotropic etch to broaden the opening. This segmentation allows each etching step to optimize for its specific function without compromise.
Solution Approach 2:
The bias voltage parameter is changed between etching steps - high bias for anisotropic etching to control fin width, then low bias for isotropic etching to broaden the opening. This parameter change enables the process to achieve both precise fin dimensions and adequate conductive material volume.
2Productivity
If device scaling is continued to increase device density, then productivity and device density are improved, but fabrication challenges and manufacturing precision difficulties increase
Solution Approach 1:
The etching process uses dynamic adjustment of bias voltage to adapt to different etching requirements at each stage. The system transitions from high bias to low bias, allowing the process to maintain manufacturing precision while achieving the desired device density through controlled structural modification.
3Productivity
If conductive feature dimensions are reduced to increase device density, then device density is improved, but electrical resistance increases and performance deteriorates
Solution Approach 1:
Instead of only reducing horizontal dimensions for scaling, the process modifies the vertical and lateral dimensions of the opening separately. The low bias isotropic etch broadens the opening horizontally while the fin height remains controlled, creating additional dimensional space for conductive material without increasing the fin footprint, thus maintaining device density while improving electrical resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of microelectronic devices with improved control over conductive structures, reduced row hammer effects, and lower write recovery times, while maintaining the structural integrity and performance of memory devices, allowing for more efficient and reliable operation.
Implementation Method 1
exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench
Implementation Method 2
exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure
Data Source
AI summary
A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.