Silicon-to-Silicon Fusion Bonding for Electro-Optical Chip Assembly

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Solution Overview

Problem

Existing optical data communication systems face challenges in reliably and efficiently connecting optical fibers to electro-optical semiconductor chips, and there is a need to test the electrical and photonic operation of these chips before physical connection to prevent inoperable components from causing losses.

Innovation Solution

The solution involves an electro-optical chip assembly with a silicon baseplate and an electro-optical chip, where the silicon substrate of the chip is fusion bonded to the baseplate. This assembly allows for the secure attachment of optical fibers and enables photonic and electronic testing before final bonding to an electronic package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If electro-optical chips are physically connected to other components before testing, then device complexity is reduced, but reliability deteriorates due to loss of inoperable components

Engineering Contradiction:
Improveconnection process complexityVSAvoidsystem reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements preliminary testing of electro-optical chips in a test socket before final assembly to other components. This allows detection and replacement of inoperable chips before they are permanently connected, resolving the contradiction by enabling reliability verification while maintaining a relatively simple final connection process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If electro-optical chips are tested before physical connection, then reliability is improved, but device complexity increases due to additional testing steps

Engineering Contradiction:
Improvesystem reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the manufacturing process into distinct phases: preliminary testing in a test socket, then final assembly to components. This segmentation allows reliability verification without requiring complex integrated testing, as the testing function is separated into a simple, dedicated test socket structure.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If traditional bonding methods are used to connect optical fibers to electro-optical chips, then ease of manufacture is maintained, but reliability deteriorates due to alignment precision issues

Engineering Contradiction:
Improvemanufacturing easeVSAvoidoptical connection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an intermediary bonding structure that facilitates precise alignment between optical fibers and electro-optical chips. This intermediary structure enables reliable optical connections while maintaining manufacturing feasibility, resolving the contradiction between ease of manufacture and connection reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures reliable and efficient optical connections, allows for pre-connection testing to prevent faulty components from causing losses, and facilitates the integration of optical fibers with electro-optical chips in optical data communication systems.

Implementation Method 1

The electro-optical chip has a silicon substrate that is fusion bonded to the silicon baseplate

Methodology Applied
Scientific EffectFusion bonding: Diffusion Welding

Data Source

PatentUS20250044534A1Direct Silicon-to-Silicon Bonding for Fiber-First Packaging Process
Publication Date: 2025.02.06 AYAR LABS INC
  • US20250044534A1 patent drawing
  • US20250044534A1 patent drawing
  • US20250044534A1 patent drawing

AI summary

An electro-optical chip assembly includes a silicon baseplate and an electro-optical chip. The electro-optical chip has a silicon substrate that is fusion bonded to the silicon baseplate. The electro-optical chip is manufactured separate from the silicon baseplate before fusion bonding of the silicon substrate of the electro-optical chip to the silicon baseplate.