Silicon-GaN Back-Gate Transistor Structure for Lower Parasitics
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in integrating high-density transistors with reduced parasitics and enhanced performance, particularly in combining silicon CMOS transistors with GaN power transistors, due to limitations in interconnectivity and processing compatibility between different material platforms.
Innovation Solution
The use of layer transfer integration techniques to bond silicon and GaN layers, where the silicon layer includes a transistor body and the GaN layer provides a field plate or back gate structure, allowing for tight integration and enhanced performance by leveraging the strengths of both materials, including the formation of a 2D electron gas for conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon CMOS transistors are integrated with GaN power transistors using conventional techniques, then device density and performance are improved, but processing compatibility and interconnectivity limitations arise
Solution Approach 1:
The transistor structure is segmented into two separate material layers: a silicon layer containing the transistor body and a GaN layer containing the field plate and back gate structure. This segmentation allows each material to be optimized for its specific function while avoiding processing incompatibilities that would arise from attempting to integrate both materials in a single layer.
Solution Approach 2:
The GaN layer with its conductive field plate structure is positioned beneath and surrounds portions of the silicon transistor body, creating a nested configuration where the GaN back gate structure is embedded within the overall transistor architecture. This nested arrangement enables tight integration and enhanced control while maintaining material-specific processing advantages.
2Reliability
If layer transfer integration techniques are used to bond silicon and GaN layers, then parasitics are reduced and performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The silicon and GaN layers are prepared separately with their respective structures (transistor body in silicon, field plate and back gate in GaN) before the bonding step. This preliminary preparation of each layer independently allows for optimized fabrication processes for each material system, reducing the overall manufacturing complexity despite the advanced integrated structure achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of parasitics and improved performance by allowing for dynamic control of transistors, reducing power consumption, and enhancing energy efficiency by utilizing the GaN layer's conductive properties to support silicon transistors, thereby improving overall system performance.
Implementation Method 1
allowing for tight integration and enhanced performance by leveraging the strengths of both materials, including the formation of a 2D electron gas for conductive layers
Implementation Method 2
The use of layer transfer integration techniques to bond silicon and GaN layers
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a GaN layer, where the silicon layer includes a first portion of a device, for example a transistor, and the GaN layer includes a second portion of the device. Other embodiments may be described and/or claimed.