Silicon-GaN Power Transistor Pairing for Drive Compatibility
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Solution Overview
Problem
Conventional enhancement-mode GaN transistors have limited applications due to their threshold voltage being close to the maximum gate-source voltage, while depletion-mode GaN transistors lack compatibility with existing low-voltage silicon transistor drive technologies.
Innovation Solution
A power device comprising an enhancement-mode silicon transistor and a depletion-mode gallium nitride transistor, where the transistors are coupled with specific electrical connections and additional components like electrostatic discharge protection, resistor, and voltage clamper to enhance functionality and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional enhancement-mode GaN transistors are used, then low on-resistance and fast switching speed are achieved, but the threshold voltage is close to the maximum gate-source voltage which limits applications
Solution Approach 1:
The patent combines an enhancement-mode GaN transistor and a depletion-mode GaN transistor into a single integrated device structure. The enhancement-mode transistor provides low on-resistance and fast switching, while the depletion-mode transistor provides a negative threshold voltage that enables the device to remain off at zero gate voltage, thus expanding application range and solving the threshold voltage limitation.
Solution Approach 2:
The integrated power device achieves multi-functionality by incorporating both enhancement-mode and depletion-mode GaN transistors, allowing the device to operate in both enhancement and depletion modes. This enables compatibility with various drive circuits and expands the versatility of the device for different applications while maintaining excellent switching performance.
2Ease of manufacture
If depletion-mode GaN transistors are used, then mature fabrication process and compatibility with drive technology are achieved, but the transistors lack the performance advantages of enhancement-mode devices
Solution Approach 1:
The patent merges depletion-mode GaN transistors (which have mature fabrication processes) with enhancement-mode GaN transistors (which provide superior switching performance) into a single integrated device. This combination allows the device to benefit from both the manufacturing maturity of depletion-mode devices and the excellent switching characteristics of enhancement-mode devices.
3Adaptability or versatility
If low-voltage silicon transistor and GaN transistor are coupled to form common gate and common source structure, then compatibility with existing drive technology is achieved, but electrostatic discharge damage and mistaken activation risks occur
Solution Approach 1:
The patent incorporates protection circuits and design features that proactively prevent electrostatic discharge damage and mistaken activation before they can occur. By designing the device with inherent protection mechanisms, the system prepares in advance against potential failures, ensuring reliable operation while maintaining compatibility with existing drive technology.
Data Source
AI summary
Power device and packaging thereof. For example, a power device including a silicon transistor and a gallium nitride transistor, the power device comprising: an enhancement-mode silicon transistor; and a depletion-mode gallium nitride transistor coupled to the enhancement-mode silicon transistor; wherein the enhancement-mode silicon transistor includes: a silicon substrate including a first substrate surface and a second substrate surface; a first transistor gate terminal electrically conductively connected to a transistor gate, the transistor gate being located on the first substrate surface of the silicon substrate through a dielectric layer; a first transistor source terminal electrically conductively connected to a first part of the silicon substrate through the first substrate surface; and a first transistor drain terminal electrically conductively connected to a second part of the silicon substrate through the first substrate surface.