Silicon Gate Drivers for Oxide Pixel Displays at Low Refresh Rates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing gate driver circuitry for OLED displays is challenging due to the need for robustness and efficiency in controlling display pixels, particularly in achieving low refresh rates and minimizing leakage current.
Innovation Solution
Implementing display pixels with only semiconducting oxide transistors for low refresh rates and gate driver circuitry using silicon transistors for improved robustness, utilizing a combination of shift register and output buffer circuits with isolated clock signals to ensure fast signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all pixel transistors are implemented as semiconducting oxide transistors, then low refresh rate operations are enabled, but gate driver robustness deteriorates
Solution Approach 1:
The patent applies different transistor types to different functional blocks: semiconducting oxide transistors are used in pixel circuits where low leakage is critical for low refresh rates, while silicon transistors are used in gate driver circuits where robustness and switching speed are prioritized. This localized differentiation resolves the contradiction by optimizing each block for its specific functional requirements.
Solution Approach 2:
The display circuit is segmented into distinct functional blocks (pixel circuits and gate driver circuits) that can be independently designed with appropriate transistor types. This segmentation allows the system to achieve both low refresh rate capability in pixels and robust gate driving performance without requiring a single transistor type for all functions.
2Reliability
If all gate driver transistors are implemented as silicon transistors, then gate driver robustness is improved, but low refresh rate operation capability deteriorates
Solution Approach 1:
Silicon transistors are specifically deployed in gate driver circuits where their superior switching characteristics and robustness are needed, while semiconducting oxide transistors are used in pixel circuits where low leakage current is essential for maintaining voltage during extended periods between refresh cycles. This localized assignment resolves the contradiction.
3Productivity
If semiconducting oxide transistors are used in gate drivers, then low refresh rate operation is enabled, but signal generation speed deteriorates
Solution Approach 1:
The patent recognizes that different circuit blocks have different speed requirements: gate drivers need fast switching for robust signal generation, while pixels need low leakage for low refresh rate operation. By assigning silicon transistors to gate drivers and semiconducting oxide transistors to pixels, each block operates at its optimal performance point without compromising the other.
4Reliability
If silicon transistors are used in pixels, then robustness is improved, but leakage current increases
Solution Approach 1:
Semiconducting oxide transistors are specifically chosen for pixel circuits due to their extremely low off-state leakage current, which is critical for maintaining pixel voltage during long refresh intervals. This material property directly enables low refresh rate operation without sacrificing pixel functionality or robustness.
Data Source
AI summary
A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.