Silicon-Germanium Oxidation via Cavity Inversion
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Solution Overview
Problem
The existing methods for manufacturing advanced CMOS devices with high germanium content silicon-germanium layers face low yield due to surface roughening and defect formation near the active region of small FETs, which is exacerbated by the oxidizing treatment process.
Innovation Solution
The method involves forming a cavity below the silicon-germanium layer and performing the oxidizing treatment from the cavity side, with a blocking layer on the upper surface to prevent germanium loss, allowing for increased germanium content without surface roughening, and enabling the formation of semiconductor devices with improved germanium distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If oxidizing treatment is performed on the silicon-germanium layer from the upper surface, then germanium content in the layer is increased, but surface roughening and defect formation occur near the active region of FETs
Solution Approach 1:
The patent inverts the conventional oxidizing approach by performing oxidation from the lower surface of the silicon-germanium layer rather than the upper surface. This is achieved by providing access to the lower surface through a cavity in the substrate, allowing germanium to be rejected into the layer from the bottom side, thereby avoiding surface roughening at the upper surface where the active region is located.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a cavity in the substrate to access the lower surface of the silicon-germanium layer. This dimensional change allows the oxidizing treatment to be applied from the opposite direction, separating the oxidation process from the active upper surface and preventing defect formation in the critical device region.
2Quantity of substance
If oxidizing treatment is performed at high temperature to increase germanium content, then germanium is rejected from the oxide layer, but this causes surface roughening and dislocations during annealing
Solution Approach 1:
By inverting the oxidation direction to proceed from the lower surface, the patent ensures that germanium rejection occurs away from the active region. The high-temperature oxidizing treatment that causes defect formation in conventional approaches now benefits the device by increasing germanium content without creating surface roughening or dislocations in the critical upper surface area.
3Quantity of substance
If a blocking layer is formed on the lower surface to prevent germanium loss, then germanium content is maintained, but this prevents oxidizing treatment from that surface
Solution Approach 1:
The patent segments the substrate structure by creating a cavity that provides selective access to the lower surface of the silicon-germanium layer. This segmentation allows the oxidizing treatment to reach the lower surface in specific regions while blocking layers can be selectively applied in other regions to control germanium distribution, thereby resolving the conflict between maintaining germanium content and enabling oxidizing treatment.
4Quantity of substance
If advanced CMOS devices with very small dimensions are manufactured using conventional oxidizing methods, then high germanium content is achieved, but yield is reduced due to surface roughening near active regions
Solution Approach 1:
By inverting the oxidation direction to proceed from the lower surface, the patent eliminates surface roughening and defect formation in the upper active region of small-dimension CMOS devices. This enables high germanium content to be achieved while maintaining high yield, as the critical device surfaces remain smooth and free from oxidation-induced defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of CMOS devices by preventing germanium pile-up near the active region, reducing surface roughening, and allowing for the formation of high germanium content layers suitable for advanced semiconductor devices like FETs, while maintaining the simplicity of the process.
Implementation Method 1
the lower surface of the silicon-germanium layer is subjected to the oxidizing treatment through the cavity
Implementation Method 2
germanium is rejected from the silicon(di)oxide layer formed at the surface subjected to the oxidizing treatment and is brought into the remainder of the silicon-germanium layer
Implementation Method 3
the blocking layer protects the silicon-germanium layer against the oxidizing treatment and on the other hand prevents germanium atoms from leaving the silicon-germanium layer at the side where the blocking layer is present
Data Source
AI summary
The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3). According to the invention, the blocking layer (3) is formed on the upper surface of the silicon-germanium layer (2), a cavity (5) is formed in the semiconductor body below the silicon-germanium layer (2) and the lower surface of the silicon-germanium layer (2) is subjected to the oxidizing treatment through the cavity (2). In this way, a device 10 may be obtained in which the surface of the silicon-germanium layer (2) after the oxidizing treatment does not suffer from roughening and/or germanium pile up. This enables e.g. to manufacture in particular a MOSFET on top of or in the silicon-germanium layer (2) with excellent properties and high yield.