Selective Etching of Silicon Germanium Fin Structures for Shallow Junctions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FinFET semiconductor fabrication techniques face challenges in achieving high drive currents with increasingly smaller dimensions due to limitations in material removal processes, particularly at technology nodes below 14 nm, where thermal oxidation and etching lack controllability and compatibility.
Innovation Solution
A method involving the growth of silicon germanium (SiGe) on silicon fin structures, followed by a thermal anneal to diffuse germanium into the silicon, and subsequent selective etching using gaseous hydrochloride to precisely remove the SiGe, allowing for the formation of epitaxial source and drain regions and a functional gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation and etching are used for material removal, then the process is simple and widely compatible, but controllability is lost at technology nodes below 14 nm
Solution Approach 1:
The patent introduces an intermediary material layer (such as silicon germanium or sacrificial gate material) between the fin structure and the etching process. This intermediary layer enables controlled material removal through selective etching, providing the necessary controllability at sub-14nm nodes while maintaining process compatibility. The intermediary acts as a mediator that translates the simple etching process into a precisely controllable material removal mechanism.
Solution Approach 2:
The patent utilizes parameter changes in material properties (such as composition, crystalline structure, or reactivity) to achieve selective etching. By changing the material parameters of the intermediary layer or the fin structure surface, the etching process becomes controllable through selective removal rates, enabling precise dimensional control at nanoscale nodes without increasing overall process complexity.
2Productivity
If fin structure dimensions are reduced to increase drive current, then device performance improves, but material removal controllability deteriorates
Solution Approach 1:
The patent applies local quality by creating spatial variations in material composition or structure within the fin structure. Different regions of the fin structure have different material properties (e.g., alloyed regions vs. pure silicon regions), enabling selective etching at specific locations. This local differentiation allows precise control of material removal even as overall dimensions shrink, maintaining manufacturing precision while enabling higher drive currents through reduced dimensions.
Solution Approach 2:
The patent segments the fin structure into distinct material regions (such as core fin material and surface alloyed layers) that can be selectively removed. This segmentation allows independent control of different portions of the fin structure, enabling precise material removal at sub-14nm dimensions while maintaining the integrity and functionality of the overall device for high drive current operation.
3Manufacturing precision
If alloyed regions are formed through annealing to enable selective removal, then manufacturing precision improves, but process time increases
Solution Approach 1:
The patent performs preliminary alloying or material modification during earlier process steps (such as during epitaxial growth or deposition) rather than requiring a separate, time-consuming annealing step. By preparing the material structure in advance with the desired composition gradients or alloyed regions, the selective etching can proceed immediately with high precision, reducing overall process time while maintaining manufacturing precision.
Solution Approach 2:
The patent merges the alloying process with other necessary fabrication steps (such as epitaxial growth, doping, or surface treatment) into a single integrated process sequence. This consolidation eliminates separate annealing steps, reducing total process time while achieving the necessary material composition variations for selective etching, thus improving manufacturing precision without proportionally increasing process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and controlled material removal, enhancing the formation of FinFETs with improved dimensions and performance by creating alloyed regions within the fin structure, which in turn facilitates the formation of epitaxial source and drain regions and a functional gate structure, addressing the limitations of existing techniques.
Implementation Method 1
An annealing process drives germanium from the germanium including material into the source and drain region portions of the fin structure
Implementation Method 2
The alloyed silicon and germanium portion is removed selectively to the interior portion of the fin structure comprised of silicon
Implementation Method 3
Epitaxial source regions and epitaxial drain regions are formed on the source and drain region portions of the fin structure
Data Source
AI summary
A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.