Silicon-Germanium Source Contact for 3D Memory Scaling
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Solution Overview
Problem
Three-dimensional memory devices face challenges in increasing on-current for vertical semiconductor channels as the number of word lines increases, leading to decreased performance and limited vertical scaling capabilities.
Innovation Solution
Incorporating a silicon-germanium source contact layer and/or vertical semiconductor channels to enhance electron mobility and conductivity, along with stressor pillar structures that apply tensile stress to improve channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to enhance memory capacity, then the storage density is improved, but the on-current of vertical semiconductor channels decreases leading to performance degradation
Solution Approach 1:
The patent changes the material composition of the source contact layer by incorporating silicon-germanium alloy with varying germanium concentrations. This parameter change in material composition enables higher electron mobility and conductivity, compensating for the on-current degradation caused by increased word line count while maintaining enhanced memory capacity
Solution Approach 2:
The patent employs composite material structures including silicon-germanium source contact layers combined with stressor pillar structures. The composite approach leverages the electrical conductivity enhancement from silicon-germanium and the mechanical stress modulation from stressor structures to collectively improve on-current while maintaining high memory capacity
2Productivity
If vertical scaling is pursued to increase memory density, then the number of stacked word lines is improved, but the channel performance deteriorates due to reduced on-current
Solution Approach 1:
The patent modifies physical parameters including germanium concentration in the source contact layer and dimensions of stressor pillar structures. These parameter changes are optimized to enhance electron mobility and apply appropriate tensile stress to channels, enabling vertical scaling to greater heights while maintaining channel performance
Solution Approach 2:
The stressor pillar structures act as intermediary elements that apply mechanical tensile stress to the vertical semiconductor channels. This intermediary stress application compensates for the performance degradation that would otherwise occur with increased vertical stacking, enabling higher memory density while preserving channel performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases the on-current of vertical semiconductor channels, enabling vertical scaling and stacking of more word lines, thereby enhancing the performance and capacity of three-dimensional memory devices.
Implementation Method 1
Incorporating a silicon-germanium source contact layer and/or vertical semiconductor channels to enhance electron mobility and conductivity
Implementation Method 2
stressor pillar structures that apply tensile stress to improve channel performance
Data Source
AI summary
A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.