Silicon III-N Semiconductor Integration via Release Layer
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Solution Overview
Problem
Current methods for integrating silicon and III-N semiconductor devices on a common substrate face challenges in achieving efficient fabrication and cost-effectiveness, particularly in forming hybrid wafers and isolating components without compromising the performance of either material.
Innovation Solution
The method involves growing III-N semiconductor material on a silicon substrate, forming planar isolation regions, ion implanting a second silicon substrate to create a release layer, bonding the silicon device film to the III-N semiconductor material, and removing portions to expose the III-N material for component formation, optionally using dielectric interlayers for enhanced bonding and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a Si (100)-GaN-Si hybrid wafer is fabricated by bonding SOI wafer to AlGaN/GaN on Si (111) wafer, then integration of silicon and III-N semiconductor devices is achieved, but fabrication complexity increases due to the need for selective removal of Si (100) active layer and mesa etching
Solution Approach 1:
The patent applies preliminary action by forming planar isolation regions in the III-N semiconductor material before bonding the silicon device film. This pre-prepared isolation structure eliminates the need for subsequent complex mesa etching processes, reducing fabrication complexity while maintaining device integration capability
Solution Approach 2:
The patent segments the isolation function from the bonding process by using pre-formed planar isolation regions in the III-N material. This segmentation allows the silicon device film to be bonded without requiring complex selective removal and etching steps, simplifying the overall fabrication process
2Strength
If thin layer of silicon oxide is used to enhance bonding between SOI and AlGaN/GaN wafers, then bonding strength is improved, but additional fabrication steps are required
Solution Approach 1:
The patent uses a dielectric interlayer as an intermediary between the silicon device film and III-N semiconductor material to enhance bonding. This intermediary layer provides improved bonding strength while being integrated into the bonding process itself, avoiding the need for separate silicon oxide deposition steps
3Manufacturing precision
If Si (100) active layer is selectively removed and mesa etching is performed, then device isolation is achieved, but fabrication time and process complexity increase
Solution Approach 1:
The patent performs preliminary formation of planar isolation regions in the III-N semiconductor material before bonding. This pre-established isolation structure eliminates the need for time-consuming selective removal and mesa etching steps after bonding, achieving device isolation more efficiently
Solution Approach 2:
The patent inverts the conventional approach by forming isolation regions in the III-N material before bonding rather than removing silicon material after bonding. This inverted sequence of operations achieves the same isolation result but significantly reduces fabrication time and process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the cost-effective and complex-free integration of silicon and III-N semiconductor devices, reducing fabrication complexity and enhancing the performance of both types of components by maintaining the integrity of the silicon and III-N semiconductor materials.
Implementation Method 1
A second silicon substrate with a second, different, orientation is ion implanted with a separating species to form a release layer between a silicon device film at a top surface of the second silicon substrate and a carrier wafer at a bottom of the second silicon substrate
Implementation Method 2
The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material (102) on a first silicon substrate (100) having a first orientation. A second silicon substrate (106) with a second, different, orientation has a release layer (108) between a silicon device film (110) and a carrier wafer (112). The silicon device film (110) is attached to the III-N semiconductor material while the silicon device film (110) is connected to the carrier wafer (112) through the release layer (108). The carrier wafer (112) is subsequently removed from the silicon device film (110). A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.