Silicon III-N Wafer Structure for Low-Strain Thick Substrates
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Solution Overview
Problem
Existing methods for producing semiconductor wafers with silicon and III-N layers face challenges in achieving the desired thickness and strain minimization, which affects their usability and cost-effectiveness in semiconductor manufacturing processes.
Innovation Solution
A method for producing semiconductor wafers with a disk-shaped design, comprising a silicon upper layer region and a silicon lower layer region, where a nitride layer with a III-N layer is formed on the top side, allowing for a maximum thickness of 3 mm and minimal strain, enabling easy further processing and cost-effective joining of wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor wafer thickness is increased to minimize strain and bending during nitride layer production, then the manufacturing cost increases due to joining multiple wafers, but the wafer stability and usability improve
Solution Approach 1:
The thick semiconductor wafer (≥1.2mm) is divided into an upper layer region (30-950μm thickness) and a lower layer region, where the lower layer region comprises or is made up of a silicon layer. This segmentation allows the wafer to achieve the necessary thickness for strain minimization while maintaining manufacturability through standardized joining processes.
Solution Approach 2:
Multiple silicon semiconductor wafers are joined together to form the lower layer region with increased thickness. This merging of multiple wafers achieves the desired total thickness (≥1.2mm) that provides sufficient mechanical stability and minimizes bending during nitride layer production, while using cost-effective standard thickness wafers.
2Ease of operation
If the upper layer region thickness is reduced to facilitate nitride layer production, then the ease of processing improves, but the wafer becomes more prone to bending and strain
Solution Approach 1:
The solution moves from varying the upper layer thickness to achieve stability to varying the lower layer thickness (through joining multiple wafers) while keeping the upper layer thickness in the optimal range for processing (30-950μm). This dimensional shift allows independent optimization of both processing ease and wafer stability.
3Manufacturing precision
If the semiconductor wafer thickness is increased beyond standard thicknesses, then the strain during nitride layer production is minimized, but the productivity decreases due to additional joining steps
Solution Approach 1:
The patent specifies a total thickness range of ≥1.2mm (up to 3mm) for the semiconductor wafer, which represents a parameter change from standard thin wafers. This thickness parameter minimizes strain and bending during nitride layer production. The connecting region with reduced diameter further optimizes the structure for this increased thickness while managing the additional joining steps.
Data Source
AI summary
A method for producing a semiconductor wafer comprising silicon and comprising a III-N layer, which has an upper layer region with a top side and a lower layer region with a bottom side. The semiconductor wafer having a total thickness of at least 1.2 mm, and the semiconductor wafer being divided along the total thickness into the upper and lower layer regions. The upper layer region having a peripheral marginal region, and the lower layer region having a second maximum diameter. A connecting region is formed between the upper layer region and the lower layer region. The connecting region having a third diameter, and the third diameter being smaller than the first maximum diameter, comprising producing a nitride layer comprising a III-N layer formed on the upper layer region, and generating a peripheral, edge-filleted or beveled marginal region at the upper layer region.