Silicon Interposer Thin Film Capacitor Bonding Reliability
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Solution Overview
Problem
Conventional BGA-type semiconductor packages face issues with bonding reliability between the interposer and chip components due to thermal expansion mismatches and the brittle nature of ceramic capacitors, leading to potential cracks and increased stray capacitance, especially in high-density solder ball arrangements.
Innovation Solution
A semiconductor package design featuring a silicon interposer with a thin film chip component, where the chip component is connected to the interposer using conductive bonding material and has a pad structure on a single surface, reducing stress and allowing for high-density mounting without disturbing the bump arrangement, and incorporating a resin layer for shock-absorbing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glass epoxy substrate is used as the interposer with an MLCC bypass capacitor, then the capacitor can be mounted on the semiconductor package, but thermal expansion mismatch causes cracks at joint areas
Solution Approach 1:
The patent uses a silicon interposer instead of a glass epoxy substrate, and a thin film capacitor instead of an MLCC, ensuring that all components have matching thermal expansion coefficients. This homogeneity in material properties eliminates thermal expansion mismatch and prevents cracks at joint areas during temperature cycles.
Solution Approach 2:
The patent changes the material parameters of the interposer and capacitor to have matching thermal expansion coefficients. By selecting silicon for the interposer and thin film capacitor technology, the thermal expansion parameter is standardized across all components, resolving the thermal mismatch problem.
2Reliability
If an MLCC with dog bone-type terminal structure is used, then the capacitor can be mounted, but gaps between terminal and solder balls increase risk of short-circuits and increase stray capacitance
Solution Approach 1:
The patent employs a thin film capacitor with a flat terminal structure that matches the planar geometry of the silicon interposer and solder ball array. This homogeneous geometric configuration eliminates gaps between terminals and solder balls, preventing short-circuits and minimizing stray capacitance effects.
3Reliability
If a ceramic MLCC is used, then the capacitor provides necessary electrical function, but the hard and brittle nature causes stress concentration and cracks when package warps
Solution Approach 1:
The patent changes the mechanical parameters of the capacitor by transitioning from ceramic MLCC to thin film capacitor technology. This material parameter change provides flexibility and stress absorption capability, allowing the capacitor to withstand package warping without cracking while maintaining electrical functionality.
4Device complexity
If the bypass capacitor is mounted far from the semiconductor element, then the mounting structure is simpler, but the equivalent serial inductance increases and noise reduction effect decreases
Solution Approach 1:
The patent merges the bypass capacitor directly onto the silicon interposer in close proximity to the semiconductor element. This integration combines the interposer and capacitor into a unified structure with short current paths, minimizing equivalent serial inductance and maximizing noise reduction effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances bonding reliability and electrical characteristics while maintaining a small size, reducing the equivalent serial inductance and minimizing noise, thus achieving superior noise reduction and stability.
Implementation Method 1
incorporating a resin layer for shock-absorbing characteristics
Implementation Method 2
the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material
Data Source
AI summary
A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.