Silicon Interposer and EMIB Layout for Memory Bandwidth and Yield
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Solution Overview
Problem
Current high-performance computer (HPC) architectures face limitations in memory bandwidth and yield due to the large size of CPU and DRAM dies, leading to increased product costs and suboptimal heat transfer, making them unsuitable for advanced process nodes like the 10 nm node.
Innovation Solution
The use of silicon interposers with embedded multi-die interconnect bridges (EMIBs) to electrically couple die cubes, allowing for high-density routing and integration of smaller CPU and memory dies, improving yield and thermal control while enabling the reuse of peripheral dies from previous generations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiple DRAM die are stacked side-by-side over the CPU die to increase memory bandwidth, then memory bandwidth is improved, but yield decreases and product cost increases
Solution Approach 1:
The system segments the memory architecture into multiple independent DRAM die stacked vertically over the CPU die using through-silicon vias (TSVs). This segmentation allows each DRAM die to be independently manufactured and tested, improving yield while providing high memory bandwidth through parallel access paths. The vertical stacking configuration enables memory bandwidth scaling without requiring larger lateral die areas that would reduce manufacturing yield.
Solution Approach 2:
The patent transitions from a lateral arrangement of DRAM die side-by-side with the CPU to a vertical stacking arrangement using the third dimension (height). By implementing memory stacks vertically over the CPU die using TSVs, the design achieves high memory bandwidth without increasing the lateral footprint, thereby maintaining manufacturing yield and reducing product cost while still providing parallel memory access paths.
2Use of energy by moving object
If multiple DRAM die are stacked side-by-side over the CPU die to increase memory bandwidth, then memory bandwidth is improved, but product cost increases
Solution Approach 1:
The memory system is segmented into multiple independent DRAM die that can be manufactured separately using standard manufacturing processes. Each die is independently tested and sorted, allowing defective dies to be identified before final assembly. This segmentation approach improves manufacturing efficiency and reduces waste, thereby lowering product cost while still achieving high memory bandwidth through the stacked configuration.
Solution Approach 2:
By moving the memory architecture to the vertical dimension using TSV-based stacking, the design achieves high memory bandwidth without requiring large lateral die areas. This reduces the complexity of manufacturing large-format packages and enables the use of smaller, more cost-effective manufacturing processes. The vertical stacking also allows for better heat dissipation, reducing cooling costs and improving overall manufacturing efficiency.
3Temperature
If physical spacing is provided between DRAM chips for manufacturing and thermal reasons, then heat transfer is improved, but memory bandwidth and density are reduced
Solution Approach 1:
The patent implements vertical stacking of DRAM die over the CPU die using through-silicon vias, utilizing the vertical dimension to achieve high memory density without increasing lateral footprint. This vertical arrangement maintains optimal thermal contact between the CPU die and heat spreader while providing sufficient thermal pathways through the TSV structures. The compact vertical integration eliminates the need for lateral spacing, maximizing memory bandwidth and density while maintaining effective heat transfer.
Solution Approach 2:
The through-silicon vias (TSVs) serve as thermal intermediaries that conduct heat vertically from the CPU die through the stacked DRAM die to the heat spreader. This intermediary thermal pathway enables efficient heat transfer through the stacked architecture without requiring lateral spacing between components. The TSVs provide both electrical interconnects and thermal conduction paths, resolving the conflict between high density and heat management.
Data Source
AI summary
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.