Silicon Interposer Package Layout for Heat Dissipation and Stress Relief
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently dissipating heat from semiconductor chips to mother substrates due to the presence of polyimide, which hinders effective thermal conductivity.
Innovation Solution
A semiconductor package design featuring a silicon interposer with a photosensitive resin having an opening portion, metal wiring, first and second bumps, and an underfill, allowing direct contact between the metal wiring and silicon interposer for enhanced heat dissipation, and additional dummy bumps and pads to increase heat dissipation paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If polyimide is disposed at the mother substrate to alleviate stress during bonding, then stress relief is improved, but heat dissipation from the semiconductor chip to the mother substrate deteriorates
Solution Approach 1:
The patent segments the bonding interface by introducing a stress relief layer that extends only partially under the package substrate, creating distinct zones: a stress relief zone where the stress relief layer is present, and a heat dissipation zone where direct contact between package substrate and mother substrate is maintained. This segmentation allows simultaneous stress management and thermal conduction without mutual interference
Solution Approach 2:
The stress relief layer is positioned locally beneath specific regions of the package substrate rather than uniformly across the entire bonding interface. This local placement strategy provides stress relief exactly where needed while preserving direct thermal pathways in other areas, thus resolving the contradiction between stress relief and heat dissipation
2Reliability
If polyimide is disposed at the mother substrate to alleviate stress, then bonding stability is improved, but thermal conductivity from semiconductor chip to mother substrate deteriorates
Solution Approach 1:
The bonding interface is segmented into functional zones: a stress relief zone with the stress relief layer for bonding stability, and a heat dissipation zone with direct substrate contact for thermal conductivity. This spatial segmentation allows each zone to optimize its specific function without compromising the other
Solution Approach 2:
The stress relief layer acts as a localized intermediary that mediates stress during bonding without interfering with thermal conduction pathways. By positioning it only where stress relief is needed and not across the entire bonding interface, it serves as a selective mediator that resolves the contradiction between bonding stability and thermal conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient heat dissipation from the semiconductor chip to the silicon interposer, alleviating thermal issues and stress during bonding, while maintaining mechanical strength and insulation properties.
Implementation Method 1
Heat generated by the semiconductor chip is dissipated to the silicon interposer through the opening portion in the photosensitive resin, allowing direct thermal contact between metal wiring and silicon interposer
Implementation Method 2
a package substrate and the mother substrate are bonded to each other via solder balls
Data Source
AI summary
A semiconductor package includes: a silicon interposer; a photosensitive resin disposed at the silicon interposer and including an opening portion; metal wiring disposed at the photosensitive resin and at the silicon interposer in the opening portion; a first bump disposed at the metal wiring in the opening portion; a semiconductor chip disposed above the first bump and including a pad electrically coupled to the first bump; and a second bump disposed at the metal wiring in a region that overlaps the photosensitive resin in a plan view.