Silicon Interposer Signal Integrity via Vertical Power Shielding
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Solution Overview
Problem
Conventional silicon interposers face issues with signal quality degradation due to high resistance characteristics and crosstalk between signal lines, especially at high frequencies, and increasing manufacturing costs with multi-layered wiring solutions.
Innovation Solution
A semiconductor device design featuring a silicon interposer with multiple wiring layers where signal lines are sandwiched and overlapped by power supply lines, acting as return paths and shields, reducing crosstalk and enhancing signal quality while maintaining a lower manufacturing cost by using fewer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If return path is formed within silicon substrate, then signal transmission is enabled, but signal quality is degraded at high frequencies due to high resistance
Solution Approach 1:
The invention moves the return path from the silicon substrate plane to a separate dedicated layer (silicon carbide layer or ground layer), creating a three-dimensional routing structure. This dimensional separation allows signal lines and return paths to coexist without overlapping in the same plane, reducing resistance and improving signal quality at high frequencies.
Solution Approach 2:
The invention introduces an intermediary layer (silicon carbide layer or ground layer) that serves as the return path. This intermediary structure mediates between the signal lines and the substrate, providing a low-resistance return path that improves signal transmission quality without interfering with the signal lines.
2Object-affected harmful factors
If wiring layers are made multi-layered (three or more layers) to reduce crosstalk, then crosstalk between signal lines is reduced, but manufacturing cost rises considerably
Solution Approach 1:
The invention uses vertical stacking of wiring layers (first wiring layer for signals, second wiring layer for return paths) to reduce crosstalk. By separating signal and return paths into different vertical layers with dielectric material in between, crosstalk is minimized without requiring an excessive number of layers, thus controlling manufacturing costs.
Solution Approach 2:
The invention applies different material properties and structural characteristics to different regions: signal lines are placed in the first wiring layer where they need to carry high-frequency signals, while return paths are placed in the second wiring layer with lower resistance characteristics. This local optimization reduces crosstalk without uniformly increasing complexity across the entire interposer.
3Object-affected harmful factors
If signal lines are arranged with larger gaps to reduce crosstalk, then crosstalk is reduced, but the area occupied by wiring increases
Solution Approach 1:
Instead of increasing horizontal gaps between signal lines to reduce crosstalk, the invention moves the return path to a different vertical layer. This allows signal lines to be closely spaced in the horizontal plane without increasing crosstalk, as the return paths are separated in the vertical dimension, thus minimizing the total wiring area.
Data Source
AI summary
Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.