Silicon Interposer Package With Integrated Stack Capacitors for PDN Integrity
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing size while maintaining high performance and reliability, especially in integrating multiple high-bandwidth memory (HBM) and central processing units (CPUs) within a single package, which requires a larger size to accommodate the increased thermal design power (TDP) and high-frequency signal integrity.
Innovation Solution
The semiconductor package incorporates a silicon interposer with through-silicon vias (TSVs) and integrated stack capacitors (ISCs) embedded in the build-up layers or grooves of the silicon substrate, which reduces the vertical size and improves the power distribution network (PDN) and signal integration by lowering impedance across multiple frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple high-bandwidth memory and CPUs are integrated within a single package, then performance and capacity are improved, but package size increases
Solution Approach 1:
The patent transitions from horizontal integration to vertical integration by stacking multiple semiconductor chips (memory chips and CPU) in the vertical direction using through-silicon vias and build-up layers. This allows multiple high-bandwidth memory and CPUs to be integrated within a single package without increasing the horizontal package footprint, thereby resolving the contradiction between improved performance/capacity and increased package size
Solution Approach 2:
The patent embeds integrated stack capacitors within the build-up layers and grooves of the silicon substrate, creating a nested structure where capacitors are integrated inside the existing package architecture. This nested integration provides additional power distribution functionality without increasing the overall package size, supporting the high-performance multi-chip integration
2Length of stationary object
If package size is reduced, then vertical size decreases, but power distribution network performance deteriorates
Solution Approach 1:
The patent integrates stack capacitors within the build-up layers and grooves of the silicon substrate, creating a nested power distribution structure. These integrated capacitors provide local decoupling and power stabilization close to the active devices, maintaining PDN performance even as the overall package vertical size is reduced through compact stacking
Solution Approach 2:
The patent places integrated stack capacitors at specific locations within the build-up layers and grooves near power-consuming devices. This local integration of power distribution elements ensures that power and signal integrity are maintained in critical areas, preventing PDN performance deterioration despite reduced overall package size
3Productivity
If signal integration is improved, then signal loss and electromagnetic interference increase in high-frequency domains
Solution Approach 1:
The patent uses vertical stacking with through-silicon vias to integrate signals in the vertical dimension, which can reduce horizontal signal trace lengths and associated interference. The build-up layers provide controlled impedance pathways for high-frequency signals, improving signal integration while managing electromagnetic effects through the three-dimensional architecture
Solution Approach 2:
The integrated stack capacitors embedded in the build-up layers serve as local decoupling elements that filter high-frequency noise and reduce electromagnetic interference. This nested integration of power and signal management functionality directly addresses signal loss and EMI issues in high-frequency domains while maintaining signal integration
Data Source
AI summary
Provided is a semiconductor package including a silicon substrate including a through-silicon via, a first build-up layer on a first surface of the silicon substrate, a second build-up layer on a second surface of the silicon substrate, and at least one integrated stack capacitor included in at least one of the silicon substrate, the first build-up layer, and the second build-up layer.