Silicon Interposer Testing via Conductive Glass Handler
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Solution Overview
Problem
Modern IC manufacturing processes face challenges in efficiently testing and integrating silicon interposers within 3D chip stacks, particularly in ensuring reliable electrical connectivity and power distribution across multiple layers, which affects the overall performance and yield of multi-chip stacks.
Innovation Solution
The method involves forming an interposer subassembly with interconnects extending from one surface to another, applying a non-conductive layer with selective open regions, and covering it with a conductive adhesive layer to facilitate testing and integration, allowing for both same-sided and two-sided testing approaches to ensure electrical isolation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-conductive layer is applied over the entire first surface to provide electrical isolation, then electrical isolation is improved, but accessibility to interconnects for testing and bonding is lost
Solution Approach 1:
The non-conductive layer is applied selectively rather than uniformly across the entire surface. Open regions are created at specific interconnect locations where electrical access is needed, while maintaining coverage in other areas for isolation. This local differentiation resolves the contradiction by providing electrical isolation where needed while preserving accessibility where required for testing and bonding operations.
2Measurement precision
If comprehensive testing of through-via structures is performed early in manufacturing, then defect detection is improved, but process complexity increases
Solution Approach 1:
Testing structures and access features are incorporated into the interposer during early manufacturing stages, before final assembly into the 3D chip stack. The non-conductive layer with open regions is prepared in advance to enable subsequent testing. This preliminary preparation allows comprehensive defect detection of through-via structures early in the process while avoiding the need for complex retroactive testing methods later.
3Ease of operation
If the same-sided testing method is used to simplify the testing process, then ease of operation is improved, but testing completeness may be reduced compared to two-sided testing
Solution Approach 1:
The non-conductive layer with strategically positioned open regions acts as an intermediary that enables effective same-sided testing. By providing controlled access points to specific interconnects on the same surface, this structure allows testing signals to reach through-via structures without requiring physical access from both sides of the interposer. The open regions are positioned to enable comprehensive testing of power, ground, and signal interconnects while maintaining the simplicity of same-sided testing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the testing and integration of silicon interposers by providing reliable electrical connectivity and power distribution, improving the detection of defects and reducing production costs by enabling early testing and ensuring better chip stack performance.
Implementation Method 1
a conductive adhesive layer adjacent the first surface of the interposer subassembly covering the open regions and remaining non-conductive layer portions
Data Source
AI summary
A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer. The method thus provides same-sided probe testing of the interposer. The method also provides for loading or power application to the conductive glass handler and testing of circuits and interconnects on the test side of the silicon interposer.