Silicon Interposer TSVs for High-Bandwidth Chip Packaging
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Solution Overview
Problem
The integration of system-on-chip (SoC) die and high bandwidth memory (HBM) dies in a single package is limited by the bandwidth of signal transfer, which is constrained by the number of wiring levels and line width of interconnects in the redistribution structure, typically around 10 microns.
Innovation Solution
The use of a silicon substrate interposer with through-substrate via (TSV) structures and metal interconnects embedded in dielectric material layers provides vertical and horizontal signal paths, enabling high-density interconnections between semiconductor dies and a package substrate, thereby increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional redistribution structure with 10 micron line width is used, then manufacturing is easier, but signal transfer bandwidth is limited
Solution Approach 1:
The patent introduces a silicon substrate interposer layer between the HBM dies and the package substrate, adding a vertical dimension to the interconnection architecture. This interposer enables three-dimensional stacking and vertical signal paths through TSVs, transitioning from planar two-dimensional wiring to three-dimensional interconnection, thereby dramatically increasing bandwidth without being constrained by planar line width limitations.
Solution Approach 2:
The silicon substrate interposer acts as an intermediary component that mediates the connection between HBM dies and the package substrate. It provides a dedicated interface layer with TSV structures that enable high-density vertical interconnections, serving as a buffer and transition platform that allows high-bandwidth communication without directly constraining the HBM die design or the final package substrate layout.
2Quantity of substance
If more wiring levels are added to increase bandwidth, then signal transfer bandwidth improves, but device complexity increases
Solution Approach 1:
Instead of adding more horizontal wiring levels in the planar direction, the patent utilizes the vertical dimension through the silicon substrate interposer. The TSV structures provide direct vertical pathways through the interposer, effectively reducing the need for multiple horizontal wiring levels and associated redistribution layers, thereby achieving high bandwidth with reduced overall structural complexity.
Solution Approach 2:
The interconnection function is segmented into distinct components: the HBM dies, the silicon substrate interposer with TSVs, and the package substrate. This segmentation allows each component to be optimized independently - the interposer specifically handles the high-density vertical interconnection function, while other components focus on their respective functions, thereby managing overall system complexity through functional decomposition.
3Quantity of substance
If line width is reduced below 10 microns to increase bandwidth, then signal transfer bandwidth improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent circumvents the need for reduced line width by transitioning to vertical interconnections through TSVs in the silicon substrate interposer. This vertical pathway approach eliminates the constraint of planar line width, allowing high-density interconnection achieved through vertical stacking rather than horizontal miniaturization, thereby avoiding the manufacturing precision challenges associated with sub-10-micron features.
Solution Approach 2:
The silicon substrate interposer serves as an intermediary that decouples the bandwidth requirement from the HBM die line width. The TSV structures in the interposer provide the high-density interconnection pathway, allowing the HBM dies to maintain their existing line width specifications while achieving increased overall system bandwidth through the interposer's vertical interconnection capability.
Data Source
AI summary
A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.