Silicon Interposer TSV Overlay Tolerance via Expanded Pads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The pick and place operation in fan-out wafer level packaging introduces lateral variations during die placement, leading to potential electrical disconnects or shorts between through-substrate via structures and redistribution layers, resulting in yield losses.
Innovation Solution
A fan-out silicon interposer structure with package-side metal pads that provide enhanced overlay tolerance, featuring through-silicon via structures, an epoxy molding compound interposer frame, and package-side redistribution structures to minimize alignment errors and ensure reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pick and place operation is used to position die or interposer, then manufacturing efficiency is improved, but lateral placement variations occur leading to electrical connection defects
Solution Approach 1:
The patent introduces an intermediary alignment structure consisting of alignment marks formed on the interposer and corresponding target marks on the carrier substrate. This intermediary marking system mediates between the pick-and-place operation and the final electrical connection, providing a reference framework that compensates for placement variations and enables precise alignment of through-silicon via structures with redistribution layers.
2Area of moving object
If pitch of through-substrate via structures is reduced to increase density, then area utilization is improved, but overlay tolerance decreases leading to increased defect rate
Solution Approach 1:
The patent implements preliminary formation of alignment marks and target marks before the pick-and-place operation. These pre-formed marks establish a reference framework in advance, allowing the system to compensate for subsequent placement variations. The alignment marks are formed on the interposer at defined locations, and target marks are formed on the carrier substrate, creating a pre-established alignment system that ensures reliable electrical connections even when via pitch is reduced for higher density.
3Extent of automation
If mechanical pick and place operation is used, then automation is improved, but overlay accuracy deteriorates due to mechanical variations
Solution Approach 1:
The patent replaces reliance on mechanical placement precision with an optical/mark-based alignment system. Instead of depending solely on the mechanical accuracy of the pick-and-place apparatus, the invention uses formed alignment marks and target marks that provide a reference system for optical or metrology-based alignment. This substitution of mechanical precision requirements with mark-based alignment allows automated placement while maintaining high overlay accuracy through the mark-guided positioning system.
Data Source
AI summary
An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.