Silicon Interposer TSV Power Distribution for Voltage Droop
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Solution Overview
Problem
The challenge lies in maintaining uniform voltage distribution across chips during low voltage, low power operations, as aggressive scaling leads to increased voltage variations (voltage droop), which can result in errors and improper chip function, especially in densely packed and miniaturized electronic devices.
Innovation Solution
The implementation of scalable silicon interposer configurations with through-silicon vias (TSVs) and lines, where power and ground interconnections are greater in number and size than signal interconnections, to support uniform power distribution. This configuration includes a first plane with TSVs serving as power and ground interconnections and a second plane with lines adapted for power and ground interconnections, both adjacent to the signal interconnections, to minimize voltage droop and ensure proper chip operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If aggressive scaling is implemented to reduce device size and power consumption, then power consumption is reduced, but voltage droop increases leading to operational errors
Solution Approach 1:
The power delivery network is segmented into multiple independent power rails and ground connections distributed across the chip substrate. This segmentation allows localized power management and reduces the impact of voltage droop in any single region, enabling low voltage operation while maintaining reliability across the entire device
Solution Approach 2:
Different regions of the chip substrate are provided with different numbers and configurations of power rails and ground connections based on local power consumption requirements. High-power-density regions receive more extensive power delivery infrastructure, while low-power regions use simplified configurations, optimizing both power efficiency and voltage uniformity
2Reliability
If the number of power and ground connections is increased to reduce voltage droop, then voltage uniformity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The power delivery network uses asymmetric configuration where power rails and ground connections are not uniformly distributed but rather concentrated in specific regions based on power consumption patterns. This asymmetric design achieves improved voltage uniformity without requiring a proportional increase in the total number of interconnections across the entire chip
Solution Approach 2:
The same TSV structure and interconnection methodology are used for both power/ground delivery and signal transmission. By making the TSV fabrication process universal, the patent achieves improved power distribution without adding separate manufacturing steps or structures, thereby avoiding increased device complexity
3Area of moving object
If chip pitch is reduced to increase density, then area utilization is improved, but voltage droop increases due to limited power grid size
Solution Approach 1:
The power delivery network transitions from a two-dimensional planar grid to a three-dimensional structure using through-silicon vias (TSVs) that extend vertically through the chip substrate. This dimensional change allows power and ground connections to be made at multiple levels, effectively increasing the power grid capacity without increasing the chip footprint, thereby supporting high-density configurations while maintaining reliable power distribution
Data Source
AI summary
Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections.