Silicon Interposer Chip Packaging to Prevent Warping During Thinning
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Solution Overview
Problem
Silicon interposers in chip packaging are prone to warping or rupture when thinned, especially when multiple chips are connected to a substrate, leading to structural instability.
Innovation Solution
A chip packaging method involving the formation of heterogeneous chips from multiple wafers, bonding these chips to silicon interposer plates, and encapsulating them with plastic layers to form chip micro-modules, which are then integrated into a final packaging structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the silicon interposer is thinned to reduce packaging height, then the packaging height is reduced, but the silicon interposer is prone to warp or rupture
Solution Approach 1:
The patent applies preliminary action by forming a protective structure around the silicon interposer before the thinning process. Specifically, a first protective layer is formed on the front surface of the silicon interposer, and a second protective layer is formed on the back surface, creating a protective framework that prevents warping and rupture during subsequent thinning operations. This preliminary protective measure enables the interposer to be thinned safely while maintaining structural integrity.
Solution Approach 2:
The patent employs composite materials by combining the silicon interposer with protective layers made of different materials. The first protective layer on the front surface and the second protective layer on the back surface create a composite structure that enhances the mechanical strength and stability of the silicon interposer during thinning. This composite approach allows the interposer to achieve both reduced thickness and improved reliability.
2Adaptability or versatility
If multiple chips are connected to the silicon interposer to increase integration, then the integration is enhanced, but the silicon interposer becomes more prone to warping
Solution Approach 1:
The patent applies preliminary action by establishing a protective framework around the silicon interposer before multiple chips are connected. The first protective layer formed on the front surface and the second protective layer formed on the back surface create structural support that prevents warping even as multiple chips are integrated onto the interposer, allowing high integration while maintaining stability.
Solution Approach 2:
The patent uses the concept of counterweight by forming protective layers on both the front and back surfaces of the silicon interposer. These protective layers act as counterbalancing structures that offset the warping forces generated when multiple chips are connected to the interposer, thereby maintaining structural stability during high-integration packaging.
3Volume of moving object
If the silicon interposer is thinned to improve packaging compactness, then the packaging compactness is improved, but the silicon interposer may rupture
Solution Approach 1:
The patent applies preliminary action by forming a protective structure around the silicon interposer before the thinning process. The first protective layer on the front surface and the second protective layer on the back surface are established in advance to prevent rupture during thinning, enabling the interposer to be thinned to improve compactness while maintaining sufficient structural strength.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer structure consisting of the silicon interposer and protective layers. This composite structure enhances the strength of the silicon interposer during thinning operations, allowing the interposer to be thinned for improved compactness without risking rupture, as the protective layers provide the necessary mechanical support.
Data Source
AI summary
A chip packaging method and a chip packaging structure are provided. The method includes: providing a carrier and wafers, where at least one wafer is different from others; cutting each wafer to form chips; selecting target chips from the chips to form chipsets, and fixing functional surfaces of the chipsets to the carrier; forming a first plastic encapsulation layer on a side of the chipsets away from the carrier and removing the carrier; forming silicon interposer plates and bonding the silicon interposer plates to the chipsets; cutting the silicon interposer plates and the chipsets to form chip micro-modules each of which includes one chipset; fixing a side of the silicon interposer plates to the carrier and forming a second plastic encapsulation layer on a side of the chip micro-modules away from the carrier; and removing the carrier and cutting the second plastic encapsulation layer, to form independent packaging structures.


