Silicon Layer Deposition for 3D NAND Conductivity
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Solution Overview
Problem
In the manufacturing of 3D NAND devices, forming a silicon layer on a substrate to cover gaps in bilayers is critical for electrical properties, but existing methods lack efficiency in achieving uniform and conductive layers with optimal electrical conductance.
Innovation Solution
A method involving positioning a substrate in a processing chamber, heating it to specific temperatures, and introducing silicon-containing precursors like trisilane or disilane to deposit layers, followed by annealing to form epitaxial grains, which improves the electrical conductance of the silicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deposition methods are used to form silicon layers, then the layer can be deposited, but the electrical conductance and uniformity are insufficient
Solution Approach 1:
The patent applies parameter changes by systematically varying deposition temperature (300-600°C range), precursor type (trisilane, disilane, silane), pressure conditions, and deposition rate to optimize the silicon layer properties. This resolves the contradiction by finding parameter combinations that achieve both high electrical conductance through proper crystallization and uniformity through controlled deposition kinetics
Solution Approach 2:
The patent employs preliminary action through substrate preparation steps including cleaning, surface treatment, and pre-heating to optimal temperature ranges before deposition. This preliminary conditioning of the substrate ensures that the subsequently deposited silicon layer achieves uniform nucleation and growth, simultaneously improving both uniformity and electrical conductance
2Reliability
If deposition temperature is increased to improve layer quality, then electrical properties improve, but energy consumption increases
Solution Approach 1:
The patent optimizes the deposition temperature parameter to specific ranges (300-600°C) that balance layer quality with energy efficiency. By identifying optimal temperature windows where sufficient thermal energy activates proper silicon crystallization without excessive energy input, the patent resolves the contradiction between achieving high electrical conductance and minimizing energy consumption
Solution Approach 2:
The patent employs plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) techniques that use chemical activation and controlled precursor reactions rather than relying solely on high thermal energy. This substitution reduces the mechanical/thermal energy input required while still achieving proper layer crystallization and electrical conductance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively forms conductive silicon layers with improved electrical properties, enhancing the functioning of 3D NAND devices by achieving uniformity and high conductivity across the layers.
Implementation Method 1
heating the substrate to a first temperature between 300 and 500° C.
Implementation Method 2
introducing a first precursor into the processing chamber to deposit a first layer
Implementation Method 3
heating the substrate to a third temperature between about 600 and 1200° C. to anneal the layer provided with silicon
Implementation Method 4
The layer may comprise epitaxial grains after heating the processing chamber to the third temperature
Data Source
AI summary
A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.